Differential plate line screen test for ferroelectric latch circuits
First Claim
1. A method of testing a non-volatile latch circuit in an integrated circuit, the latch circuit comprising cross-coupled inverters driving first and second storage nodes, a first ferroelectric capacitor having a first plate coupled to the first storage node, and a second ferroelectric capacitor having a first plate coupled to the second storage node, the method comprising:
- setting the state of the latch circuit so that the first and second storage nodes are at low and high logic states, respectively;
then polarizing the first and second ferroelectric capacitors to opposite polarization states, corresponding to the state of the latch circuit, by applying low and high bias voltages to a second plate of the first ferroelectric capacitor and a second plate of the second ferroelectric capacitor;
then removing bias from the cross-coupled inverters of the latch circuit;
then biasing the second plate of the first ferroelectric capacitor to a first bias voltage, and biasing the second plate of the second ferroelectric capacitor to a second bias voltage, the second bias voltage lower than the first bias voltage by a selected differential;
then applying bias to the cross-coupled inverters of the latch circuit; and
then reading the state of the latch circuit.
0 Assignments
0 Petitions
Accused Products
Abstract
Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.
-
Citations
10 Claims
-
1. A method of testing a non-volatile latch circuit in an integrated circuit, the latch circuit comprising cross-coupled inverters driving first and second storage nodes, a first ferroelectric capacitor having a first plate coupled to the first storage node, and a second ferroelectric capacitor having a first plate coupled to the second storage node, the method comprising:
-
setting the state of the latch circuit so that the first and second storage nodes are at low and high logic states, respectively; then polarizing the first and second ferroelectric capacitors to opposite polarization states, corresponding to the state of the latch circuit, by applying low and high bias voltages to a second plate of the first ferroelectric capacitor and a second plate of the second ferroelectric capacitor; then removing bias from the cross-coupled inverters of the latch circuit; then biasing the second plate of the first ferroelectric capacitor to a first bias voltage, and biasing the second plate of the second ferroelectric capacitor to a second bias voltage, the second bias voltage lower than the first bias voltage by a selected differential; then applying bias to the cross-coupled inverters of the latch circuit; and then reading the state of the latch circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
Specification