Semiconductor memory having both volatile and non-volatile functionality and method of operating

• US 8,472,249 B2
• Filed: 09/27/2011
• Issued: 06/25/2013
• Est. Priority Date: 10/24/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Tuan T
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US13/246,582
• Publication Number:
  US 20120014180A1
• Time in Patent Office: 637 Days
• Field of Search: 365/185.08, 365/185.17, 365/149, 365/150
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/7887 : Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 : Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/056 : the transistor being a FinFET
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 : the transistor being a FinFET
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 : Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Claims

1. A method of operating a semiconductor storage device comprising a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory, a buried layer beneath said floating body, and a floating gate or trapping layer above said floating body for storing data as non-volatile memory, the method comprising:

reading and storing data to the floating bodies as volatile memory while power is applied to the device;

transferring the data stored in the floating bodies, by a parallel, non-algorithmic process, to the floating gates or trapping layers corresponding to the floating bodies, when power to the device is interrupted; and

storing the data in the floating gates or trapping layers as non-volatile memory.

2. The method of claim 1, further comprising:

transferring the data stored in the floating gates or trapping layers, by a parallel, non-algorithmic restore process, to the floating bodies corresponding to the floating gates or trapping layers, when power is restored to the cell;

and storing the data in the floating bodies as volatile memory.

3. The method of claim 2, further comprising restoring the floating gates or trapping layers to a predetermined charge state after the restore process.

4. The method of claim 2, further comprising writing a predetermined state to the floating bodies prior to the transferring the data stored in the floating gates or trapping layers to the floating bodies.

5. The method of claim 4, wherein the predetermined state is state “

0”

.

6. The method of claim 1, further comprising initializing the floating gates or trapping layers, to each have the same predetermined state prior to the transferring.

7. The method of claim 6, wherein the predetermined state comprises a positive charge.

8. The method of claim 1, wherein the data transferred is stored in the floating gates or trapping layers with charges that are complementary to charges of the floating bodies when storing the data.

9. A method of selecting a semiconductor memory cell in a string, comprising a plurality of semiconductor memory cells each having a floating body for storing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory, the method comprising:

selecting at least one of said semiconductor memory cells; and

turning on at least one passing cell in said string, wherein each said passing cell is a cell not having been selected in said string.

10. The method of claim 9, further comprising reading said at least one selected memory cell during a volatile mode operation.

11. The method of claim 9, further comprising writing said at least one selected memory cell during a volatile mode operation.

12. The method of claim 9, wherein each said memory cell in said string includes a control gate, said method further comprising applying a voltage to the control gates, wherein voltage applied to said control gates of said passing cells is greater than voltage applied to said control gate of said at least one selected cell.

13. A method of operating a semiconductor device to economize power usage, wherein said semiconductor device comprises a string of memory cells each having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory, the method comprising:

monitoring activity of at least one of said cells; and

after a predetermined period of time during which said at least one cell has remained idle, performing a shadowing operation thereby storing a state of said at least one cell in said non-volatile memory.

14. The method of claim 13, wherein said monitoring comprises monitoring activity of each of said memory cells.

15. The method of claim 13, further comprising:

shutting down power to said memory string.

16. The method of claim 13, further comprising:

shutting down power to the volatile memory of said floating body of said at least one memory cell.

17. The method of claim 13, wherein said at least one cell comprises at least two cells and said shadowing operation occurs in a parallel, non-algorithmic manner.

18. The method of claim 13, further comprising:

restoring a volatile memory state into said floating body of each of said at least one cells, respectively, when said volatile memory data is needed, wherein said volatile memory state is the same as a volatile memory state stored in said floating body before performing said shadowing operation.