Method and apparatus for failure analysis of semiconductor integrated circuit devices

• US 8,472,695 B2
• Filed: 07/23/2009
• Issued: 06/25/2013
• Est. Priority Date: 07/28/2008
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Nikaido, Masafumi
• Primary Examiner(s): Zeender, Ryan
• Assistant Examiner(s): CHEIN, ALLEN C
• Application Number:
  US12/458,825
• Publication Number:
  US 20100021049A1
• Time in Patent Office: 1,433 Days
• Field of Search: None
• US Class Current: 382/145
• CPC Class Codes: G01R 31/2839 using signal generators, power supplies or circuit analysers G01R31/2879 takes precedence; multimeters G01R15/12, network analysers G01R27/28
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G06T 2207/10056 Microscopic image
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0006 using a design-rule based approach
• CPC Class Codes: G06V 10/25 Determination of region of interest [ROI] or a volume of interest [VOI]

Abstract

A method of analyzing of a semiconductor integrated circuit includes inspecting a physical defect in a semiconductor wafer, subjecting the semiconductor integrated circuit chip to a logic test and extracting a malfunctioning chip, analyzing a detected signal observed from the malfunctioning chip by an analyzer, obtaining the layer and coordinates of a circuit related the detected signal, collating the physical defect with the circuit, and identifying the physical defect associated with the circuit. The layer and coordinates of the circuit is extracted using design data. An inspection step identifying information is collated with the layer of the circuit, and an in-chip coordinates of the physical defect is collated with the coordinated of the circuit.

Claims

1. A method of analyzing a failure of a semiconductor integrated circuit chip, said method comprising:

inspecting a physical defect in a semiconductor wafer, by a visual inspection apparatus, at a time of manufacture of a semiconductor integrated circuit chip,

acquiring, by the visual inspection apparatus, a chip position with respect to the semiconductor wafer identifying information of said physical defect and in-chip coordinates of the physical defect in an inspection step;

subjecting the semiconductor integrated circuit to a logic test by a chip selecting unit, wherein the logic test comprises test data input into a chip under test;

extracting, by the chip selecting unit, a malfunctioning chip and a position of said malfunctioning chip on the semiconductor wafer based on the logic test;

analyzing, by a signal detecting unit, a detected signal observed from the malfunctioning chip based on the test data input into the malfunctioning chip;

acquiring, by the signal detecting unit, circuit coordinates and a layer of the detected signal;

extracting, by a circuit extracting unit, a layer and circuit coordinates in a design layout, with regard to a cell in which the detected signal was detected and a net connected to said cell, or a net in which the detected signal was detected and a cell connected to said net, using design data and the circuit coordinates and layer of the detected signal;

collating, by a collating unit, the chip position with respect to the semiconductor wafer, the layer of the circuit in the design layout, the in-chip coordinates of the physical defect from the inspection step and the circuit coordinates in the design layout from the extracting unit; and

identifying, by the collating unit, the physical defect associated with the malfunctioning chip from the collating.

2. The method according to claim 1, further comprising:

acquiring an image that includes the detected signal; and

displaying the image and layout design data in superimposed form to extract a layer and circuit coordinates of the detected signal.

3. The method according to claim 1, further comprising:

expanding circuit coordinates into a nearby specific zone to be collated with the in-chip coordinates of the physical defect.

4. The method according to claim 1, wherein in a case where the circuit coordinates reside in a specific region near a physical defect, said physical defect is extracted and collated with the circuit.

5. The method according to claim 1, wherein said extracting the layer and circuit coordinates in the design layout comprises, using the design data, extracting the layer and circuit coordinates with regard to a cell in a specific zone near the detected signal and a net connected to said cell, or a net passing through the layer of the detected signal and located in a specific zone near the detected signal and a cell connected to said net.

6. A non-transitory computer-readable storage medium storing a program for causing a computer to execute the method of analyzing failure of a semiconductor integrated circuit set forth in claim 1.

7. The method according to claim 1, wherein the inspecting of the physical defect in a semiconductor wafer acquires a chip position with respect to the semiconductor integrated circuit.

8. The method according to claim 1, wherein the subjecting comprises subjecting of the semiconductor integrated circuit to the logic test in the semiconductor wafer and extracting the malfunctioning chip and a position of said chip.

9. The method according to claim 1, wherein the analyzing of the detected signal is input to the semiconductor integrated circuit chip from the logic test.

10. The method according to claim 1, wherein the extracting of the layer and the circuit coordinates in the design layout is with regard to the cell in which the detected signal was detected and a net connected to said cell using design data and the coordinates and layer of the detected signal.

11. An apparatus including a processor and a non-transitory memory for analyzing failure of a semiconductor integrated circuit, said apparatus comprising:

a visual inspection apparatus that acquires, at a time of manufacture of a semiconductor integrated circuit chip, in-chip coordinates of the physical defect and a chip position with respect to the semiconductor wafer in an inspection step;

a chip selecting unit that subjects a semiconductor integrated circuit chip to a logic test based upon test data, and outputs selection data including a chip position of a malfunctioning chip in a semiconductor wafer, wherein the logic test comprises test data input into a chip under test;

a signal detecting unit, which includes an analyzer, that analyzes a detected signal from the test data, which has been observed from the malfunctioning chip, by the analyzer, and outputs detected signal data including circuit coordinates and a layer of the detected signal;

a circuit extracting unit that reads design data and the circuit coordinates and the layer of the detected signal and extracts a layer and circuit coordinates in a design layout, with regard to a cell in which the detected signal was detected and a net connected to said cell, or a net in which the detected signal was detected and a cell connected to said net, and outputs the layer and the circuit coordinates in the design layout;

a collating unit that collates;

the chip position with respect to the semiconductor wafer;

the in-chip coordinates of the physical defect;

the layer and the circuit coordinates in the design layout, and

correspondence between the in-chip coordinates of the physical defect, the chip position with respect to the semiconductor wafer and the layer in the design layout.

and based on the collation identifies the physical defect data associated with the circuit extracted by said circuit extracting unit, and outputs said data as collation-result data,

and

a display unit that displays the collation-result data.

12. The apparatus according to claim 11, wherein said signal detecting unit outputs image data that includes a detected signal;

and

said circuit extracting unit superimposes the image data and layout design data, and extracts the circuit and outputs the circuit as circuit extraction data.

13. The apparatus according to claim 11, wherein said collating unit collates an inspection step of a physical defect with the layer of the circuit extracted from the detected signal, based upon the inspection step/layer correspondence data, the inspection step identifying information of the physical defect data and the layer of the circuit extraction data, expands the circuit coordinates into a nearby specific zone and performs the collation to determine whether there is an overlap with the in-chip coordinates of the physical defect, thereby collating the coordinates of the physical defect with the circuit coordinates in the design layout.

14. The apparatus according to claim 11, wherein said collating unit collates an inspection step of a physical defect with the layer of the circuit extracted from the detected signal, based upon the inspection step/layer correspondence data, the inspection step identifying information of the physical defect data, and the layer of the circuit extraction data, expands the in-chip coordinates of the physical defect into a nearby specific zone and collates coordinates of said nearby specific zone with the circuit coordinates in the design layout.

15. The apparatus according to claim 11, wherein said circuit extracting unit, using the design data, extracts the layer and circuit coordinates in the design layout, with regard to a cell in a specific zone near the detected signal and a net connected to said cell, or a net passing through the layer of the detected signal and located in a specific zone near the detected signal and a cell connected to said net.

16. A non-transitory computer-readable storage medium storing a program for causing a computer to function as the apparatus for analyzing failure of a semiconductor integrated circuit set forth in claim 11.

17. The apparatus according to claim 11, wherein a processor of a computer includes the chip selecting unit, the signal detecting unit, the circuit extracting unit, and the collating unit.

18. A non-transitory computer-readable storage medium storing a program for causing a computer to execute a failure analysis processing, the processing comprising:

inspecting a physical defect in a semiconductor wafer, by a visual inspection apparatus, at a time of manufacture of a semiconductor integrated circuit chip,

acquiring, by the visual inspection apparatus, a chip position with respect to the semiconductor wafer, an inspection step identifying information of said physical defect and in-chip coordinates of the physical defect in an inspection step;

subjecting the semiconductor integrated circuit to a logic test by a chip selecting unit, wherein the logic test comprises test data input into a chip under test;

signal detection processing that extracts detected signal data based on the test data input into the chip that includes circuit coordinates and a layer from a detected signal from analytical data that is a result of failure analysis of a semiconductor integrated circuit by an analyzer;

circuit extraction processing, by a circuit extracting unit, that includes inputting design data of the semiconductor integrated circuit and the detected signal data, extracting a layer and circuit coordinates in a design layout, with regard to a cell in which the detected signal was detected and a net connected to said cell, or a net in which the detected signal was detected and a cell connected to said net, and outputting the layer and circuit coordinates in the design layout as circuit extraction data;

collation processing, by a collating unit, that includes collating the chip position with respect to the semiconductor wafer, the in-chip coordinates of the physical defect, the layer and the circuit coordinates in the design layout, and correspondence between the in-chip coordinates of the physical defect, the chip position with respect to the semiconductor wafer and the layer in the design layout, and based on the collation, identifying the physical defect data associated with the circuit extracted by said circuit extraction processing, and outputting said data as collation-result data;

and

display processing that displays the collation-result data.