Terahertz phased array system

• US 8,472,884 B2
• Filed: 09/09/2010
• Issued: 06/25/2013
• Est. Priority Date: 09/09/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ginsburg, Brian P., Rentala, Vijay B., Ramaswamy, Srinath M., Haroun, Baher S., Seok, Eunyoung
• Primary Examiner(s): Dao, Minh D
• Application Number:
  US12/878,484
• Publication Number:
  US 20120062286A1
• Time in Patent Office: 1,020 Days
• Field of Search: 455/67.16, 455/276.1, 455/304, 455/23, 455/139, 455/180.3, 455/205, 455/225, 343/702, 343/853, 343/778, 250/340
• US Class Current: 455/67.16
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 3/26 varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture H01Q3/12, H01Q3/22, H01Q3/24 take precedence
• CPC Class Codes: H03B 2200/0074 Locking of an oscillator by injecting an input signal directly into the oscillator
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

Microelectronics have now developed to the point where radiation within the terahertz frequency range can be generated and used. Here, an integrated circuit or IC is provided that includes a phased array radar system, which uses terahertz radiation. In order to accomplish this, several features are employed; namely, a lower frequency signal is propagated to transceivers, which multiplies the frequency up to the desired frequency range. To overcome the losses from the multiplication, an injection locked voltage controlled oscillator (ILVCO) is used, and a high frequency power amplifier (PA) can then be used to amplify the signal for transmission.

Claims

1. An apparatus comprising:

a local oscillator that generates a local oscillator signal and a pulse signal;

a distribution network that is coupled to the local oscillator so as to at least distribute the local oscillator signal;

a plurality of transceivers, wherein each transceiver has a radiator, a transmit path that is coupled to the radiator, and a receive path that is coupled to the radiator, and wherein the transmit path for each transceiver includes;

a phase shifter is coupled to the distribution network so as to receive the local oscillator signal;

a multiplier that is coupled to the phase shifter so as to receive a phase shifted local oscillator signal;

a injection-locked voltage controlled oscillator (ILVCO) that is coupled to the multiplier; and

a power amplifier (PA) that is coupled to the ILVCO and that receives the pulse signal; and

receiver circuitry that is coupled to the receive path for each of the transceivers.

2. The apparatus of claim 1, wherein the local oscillator signal further comprises a first local oscillator signal, and wherein the local oscillator further comprises:

a phase locked loop (PLL) that receives a reference signal and that generates the first oscillator signal and a second local oscillator signal;

a counter that receives a control signal and that is coupled to the PLL; and

a pulse generator that is coupled to the counter and the PLL, wherein the pulse generator generates the pulse signal based at least in part on the second local oscillator signal and an output from the counter.

3. The apparatus of claim 2, wherein the PLL further comprises:

a phase detector that receives the reference signal;

a charge pump that is coupled to the phase detector;

a low pass filter that is coupled to the charge pump;

a voltage controlled oscillator (VCO) that is coupled to the low pass filter;

an amplifier that is coupled to the VCO; and

a plurality of dividers that are coupled in series with one another between the VCO and the phase detector.

4. The apparatus of claim 2, wherein the transmit path for each transceiver further comprises an amplifier that is coupled between the phase shifter and the multiplier.

5. The apparatus of claim 4, wherein the ILVCO further comprises:

a first node;

a second node;

an inductive network that is coupled between the first and second nodes;

a capacitive network that is coupled between the first and second nodes;

a first MOS transistor that is coupled to the first node at its source or its drain and to the second node at its gate;

a second MOS transistor that is coupled to the second node at its source or its drain and to the first node at its gate;

a third MOS transistor that is coupled generally in parallel to the first MOS transistor;

a fourth MOS transistor that is coupled generally in parallel to the second MOS transistor; and

a balun that is coupled to the amplifier and that is coupled to the gates of the third and fourth MOS transistors.

6. The apparatus of claim 5, wherein the PA further comprises:

a first capacitor that receives an output from the ILVCO;

a first inductor that is coupled to the first capacitor;

a second inductor that is coupled to the first inductor;

a second capacitor that is coupled to the second inductor;

a third inductor;

a fifth MOS transistor that is coupled to the first and second inductor at its gate and that is coupled to the third inductor;

a fourth inductor;

a fifth inductor;

a sixth MOS transistor that receives the pulse signal at its gate and that is coupled between the fourth and fifth inductors; and

a third capacitor that is coupled between the third and fifth inductors.

7. The apparatus of claim 4, wherein the amplifier further comprises a first amplifier, and wherein the multiplier further comprises a first multiplier, and wherein the receive path for each transceiver further comprises:

a low noise amplifier (LNA) that is coupled to the radiator;

a second multiplier that is coupled to the first amplifier;

a second amplifier that is coupled to second multiplier;

a mixer that is coupled to the LNA and the second amplifier; and

a third amplifier that is coupled to the mixer.

8. The apparatus of claim 7, wherein the mixer further comprises a first mixer, and wherein the receive path for each transceiver further comprises:

a second mixer that is coupled to the first and third amplifiers; and

a fourth amplifier that is coupled to the second mixer.

9. The apparatus of claim 4, wherein the amplifier further comprises a first amplifier, and wherein the transmit path for each transceiver further comprises a flip-flop that receives the pulse signal and that is coupled to the first amplifier, the ILVCO, and the PA, and wherein the multiplier further comprises a first multiplier, and wherein the receive path for each transceiver further comprises:

an LNA that is coupled to the radiator;

a second amplifier that is coupled to the ILVCO;

a mixer that is coupled to the LNA and the second amplifier; and

a third amplifier that is coupled to the mixer.

10. The apparatus of claim 1, wherein each phase shifter further comprises:

a first input terminal;

a second input terminal;

a first inductor that is coupled to the first input terminal;

a second inductor that is coupled to the second input terminal; and

a plurality of phase shifters, wherein each phase shifter includes;

a first MOS transistor that is coupled to the first input terminal at its drain;

a second MOS transistor that is coupled to the second input terminal at its drain; and

a third MOS transistor that is coupled to the sources of the first and second MOS transistors at its drain.

11. The apparatus of claim 10, wherein the multiplier further comprises:

a differential choke;

a rectifying interleaver that is coupled to the differential choke; and

a VCO that is coupled to the rectifying interleaver.

12. The apparatus of claim 1, wherein the receiver circuitry further comprises:

a summing circuit that is coupled to the receive path for each transceiver;

an amplifier that is coupled to the summing circuit;

a filter that is coupled to the amplifier; and

digitization circuit that is coupled to the amplifier.

13. The apparatus of claim 12, wherein the local oscillator signal further comprises a first local oscillator signal, and wherein the local oscillator generates a second local oscillator signal, and wherein the receiver circuit further comprises a mixer that is coupled between the summing circuit and the amplifier and that receives the second local oscillator signal.

14. An apparatus comprising:

a local oscillator including;

a phase detector that receives a reference signal;

a charge pump that is coupled to the phase detector;

a low pass filter that is coupled to the charge pump;

a local oscillator VCO that generates a first local oscillator signal having that is greater than 40 GHz;

a plurality of dividers coupled in series with one another between the local oscillator VCO and the phase detector so as to provide a feedback signal to the phase detector that is generated from the first local oscillator signal, wherein the at least one of the plurality of dividers generates a second local oscillator having a frequency that is greater than 20 GHz;

a counter that receives the feedback signal and a control signal; and

a pulse generator that receives the second local oscillator signal, that is coupled to the counter, and that generates a pulse signal;

a distribution network that is coupled to the local oscillator so as to at least distribute the first local oscillator signal;

a plurality of transceivers, wherein each transceiver has a radiator, a transmit path that is coupled to the radiator, and a receive path that is coupled to the radiator, and wherein the radiators are arranged into an array, and wherein the transmit path for each transceiver includes;

a phase shifter is coupled to the distribution network so as to receive the first local oscillator signal;

a multiplier that is coupled to the phase shifter so as to receive a phase shifted first local oscillator signal;

an ILVCO having;

a first node;

a second node;

an inductive network that is coupled between the first and second nodes;

a capacitive network that is coupled between the first and second nodes;

a first MOS transistor that is coupled to the first node at its source or its drain and to the second node at its gate;

a second MOS transistor that is coupled to the second node at its source or its drain and to the first node at its gate;

a third MOS transistor that is coupled generally in parallel to the first MOS transistor;

a fourth MOS transistor that is coupled generally in parallel to the second MOS transistor; and

a balun that is coupled to the first multiplier and the gates of the third and fourth MOS transistors;

a PA that is coupled to the ILVCO and its radiator and that receives the pulse signal; and

receiver circuitry that is coupled to the receive path for each of the transceivers.

15. The apparatus of claim 14, wherein the PA further comprises:

a first capacitor that receives an output from the ILVCO;

a first inductor that is coupled to the first capacitor;

a second inductor that is coupled to the first inductor;

a second capacitor that is coupled to the second inductor;

a third inductor;

a fifth MOS transistor that is coupled to the first and second inductor at its gate and that is coupled to the third inductor;

a fourth inductor;

a fifth inductor;

a sixth MOS transistor that receives the pulse signal at its gate and that is coupled between the fourth and fifth inductors; and

a third capacitor that is coupled between the third and fifth inductors.

16. The apparatus of claim 15, wherein the receiver circuitry further comprises:

a summing circuit that is coupled to the receive path for each transceiver;

an amplifier that is coupled to the summing circuit;

a filter that is coupled to the amplifier; and

digitization circuit that is coupled to the amplifier.

17. The apparatus of claim 16, wherein the receiver circuit further comprises a mixer that is coupled between the summing circuit and the amplifier and that receives the second local oscillator signal.

18. An apparatus comprising:

a plurality of radiators that are arranged in a pattern for form an array;

a local oscillator that generates a local oscillator signal and a pulse signal;

a distribution network that is coupled to the local oscillator so as to at least distribute the local oscillator signal;

a plurality of transmitter paths, wherein each transmitter path is coupled between the distribution network and at least one of the radiators, and wherein each transmit path includes;

a phase shifter is coupled to the distribution network so as to receive the local oscillator signal;

a multiplier that is coupled to the phase shifter so as to receive a phase shifted local oscillator signal;

an ILVCO that is coupled to the multiplier; and

a PA that is coupled to the ILVCO and that receives the pulse signal; and

a plurality of receiver paths, wherein each receiver path is coupled to at least one of the radiators;

receiver circuitry that is coupled to each receive path; and

a controller that is coupled to each phase shifter.

19. The apparatus of claim 18, wherein the local oscillator signal further comprises a first local oscillator signal, and wherein the local oscillator further comprises:

a PLL that receives a reference signal and that generates the first local oscillator signal and a second local oscillator signal;

a counter that receives a control signal and that is coupled to the PLL; and

a pulse generator that is coupled to the counter and the PLL, wherein the pulse generator generates the pulse signal based at least in part on the second local oscillator signal and an output from the counter.

20. The apparatus of claim 19, wherein the PLL further comprises:

a phase detector that receives the reference signal;

a charge pump that is coupled to the phase detector;

a low pass filter that is coupled to the charge pump;

a VCO that is coupled to the low pass filter;

an amplifier that is coupled to the VCO; and

a plurality of dividers that are coupled in series with one another between the VCO and the phase detector.

21. The apparatus of claim 20, wherein each transmit path further comprises an amplifier that is coupled between the phase shifter and the multiplier.

22. The apparatus of claim 21, wherein the ILVCO further comprises:

a first node;

a second node;

an inductive network that is coupled between the first and second nodes;

a capacitive network that is coupled between the first and second nodes;

a first MOS transistor that is coupled to the first node at its source or its drain and to the second node at its gate;

a second MOS transistor that is coupled to the second node at its source or its drain and to the first node at its gate;

a third MOS transistor that is coupled generally in parallel to the first MOS transistor;

a fourth MOS transistor that is coupled generally in parallel to the second MOS transistor; and

a balun that is coupled to the amplifier and the gates of the third and fourth MOS transistors.

23. The apparatus of claim 22, wherein the PA further comprises:

a first capacitor that receives an output from the ILVCO;

a first inductor that is coupled to the first capacitor;

a second inductor that is coupled to the first inductor;

a second capacitor that is coupled to the second inductor;

a third inductor;

a fifth MOS transistor that is coupled to the first and second inductor at its gate and that is coupled to the third inductor;

a fourth inductor;

a fifth inductor;

a sixth MOS transistor that receives the pulse signal at its gate and that is coupled between the fourth and fifth inductors; and

a third capacitor that is coupled between the third and fifth inductors.

24. The apparatus of claim 21, wherein the amplifier further comprises a first amplifier, and wherein the multiplier further comprises a first multiplier, and wherein each receive path further comprises:

a low noise amplifier (LNA) that is coupled to the radiator;

a second multiplier that is coupled to the first amplifier;

a second amplifier that is coupled to second multiplier;

a mixer that is coupled to the LNA and the second amplifier; and

a third amplifier that is coupled to the mixer.

25. The apparatus of claim 24, wherein the mixer further comprises a first mixer, and wherein each receive path further comprises:

a second mixer that is coupled to the first and third amplifiers; and

a fourth amplifier that is coupled to the second mixer.

26. The apparatus of claim 21, wherein the amplifier further comprises a first amplifier, and wherein each transmit path further comprises a flip-flop that receives the pulse signal and that is coupled to the first amplifier, the ILVCO, and the PA, and wherein the multiplier further comprises a first multiplier, and wherein each receive path further comprises:

an LNA;

a second amplifier that is coupled to the ILVCO;

a mixer that is coupled to the LNA and the second amplifier; and

a third amplifier that is coupled to the mixer.

27. The apparatus of claim 18, wherein each phase shifter further comprises:

a first input terminal;

a second input terminal;

a first inductor that is coupled to the first input terminal;

a second inductor that is coupled to the second input terminal; and

a plurality of phase shifters, wherein each phase shifter includes;

a first MOS transistor that is coupled to the first input terminal at its drain;

a second MOS transistor that is coupled to the second input terminal at its drain; and

a third MOS transistor that is coupled to the sources of the first and second MOS transistors at its drain.

28. The apparatus of claim 27, wherein the multiplier further comprises:

a differential choke;

a rectifying interleaver that is coupled to the differential choke; and

a VCO that is coupled to the rectifying interleaver.

29. The apparatus of claim 18, wherein the receiver circuitry further comprises:

a summing circuit that is coupled to the receive path for each transceiver;

an amplifier that is coupled to the summing circuit;

a filter that is coupled to the amplifier; and

digitization circuit that is coupled to the amplifier.

30. The apparatus of claim 29, wherein the local oscillator signal further comprises a first local oscillator signal, and wherein the local oscillator generates a second local oscillator signal, and wherein the receiver circuit further comprises a mixer that is coupled between the summing circuit and the amplifier and that receives the second local oscillator signal.

31. The apparatus of claim 30, wherein the summing circuit further comprises a summing amplifier tree.