Network on chip that maintains cache coherency with invalidation messages
First Claim
1. An method for maintaining cache coherency on a network on chip (‘
- NOC’
) with invalidation messages, the NOC comprising integrated processor (‘
IP’
) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the method comprising;
sending, from an invalidating module to selected IP blocks, an invalidation message, the invalidation message representing an instruction to invalidate cached memory;
responsive to receiving the invalidation message, invalidating, by the selected IP blocks, the contents of the cached memory;
determining, by each of the selected IP blocks in dependence upon information in the invalidation message, whether to forward the invalidation message; and
if the message is to be forwarded, forwarding the invalidation message.
1 Assignment
0 Petitions
Accused Products
Abstract
A network on chip (‘NOC’), and methods of operation of a NOC, that maintains cache coherency with invalidation messages, the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC also including an invalidating module configured to send, to selected IP blocks, an invalidation message, the invalidation message representing an instruction to invalidate cached memory and the selected IP blocks, each selected IP block configured to invalidate the contents of the cached memory responsive to receiving the invalidation message.
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Citations
15 Claims
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1. An method for maintaining cache coherency on a network on chip (‘
- NOC’
) with invalidation messages, the NOC comprising integrated processor (‘
IP’
) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the method comprising;sending, from an invalidating module to selected IP blocks, an invalidation message, the invalidation message representing an instruction to invalidate cached memory; responsive to receiving the invalidation message, invalidating, by the selected IP blocks, the contents of the cached memory; determining, by each of the selected IP blocks in dependence upon information in the invalidation message, whether to forward the invalidation message; and if the message is to be forwarded, forwarding the invalidation message. - View Dependent Claims (2, 3, 4, 5)
- NOC’
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6. A network on chip (‘
- NOC’
) that maintains cache coherency with invalidation messages, the NOC comprising integrated processor (‘
IP’
) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC further comprising;an invalidating module configured to send, to selected IP blocks, an invalidation message, the invalidation message representing an instruction to invalidate cached memory; and the selected IP blocks, each selected IP block configured to invalidate the contents of the cached memory responsive to receiving the invalidation message, wherein each of the selected IP blocks is configured to determine, in dependence upon information in the invalidation message, whether to forward the invalidation message and to forward the invalidation message if the message is determined to be forwarded. - View Dependent Claims (7, 8, 9, 10)
- NOC’
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11. A computer program product for maintaining cache coherency with invalidation messages on a network on chip (‘
- NOC’
), the NOC comprising integrated processor (‘
IP’
) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the computer program product disposed in a computer-readable, recordable medium, the computer program product comprising computer program instructions for;sending, from an invalidating module to selected IP blocks, an invalidation message, the invalidation message representing an instruction to invalidate cached memory; responsive to receiving the invalidation message, invalidating, by the selected IP blocks, the contents of the cached memory; determining, by each of the selected IP blocks in dependence upon information in the invalidation message, whether to forward the invalidation message; and if the message is to be forwarded, forwarding the invalidation message. - View Dependent Claims (12, 13, 14, 15)
- NOC’
Specification