Methods and systems for power efficient instruction queue management in a data processing system

• US 8,473,764 B2
• Filed: 02/24/2012
• Issued: 06/25/2013
• Est. Priority Date: 01/07/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: de Cesare, Joshua, Semeria, Bernard, Smith, Michael
• Primary Examiner(s): TRAN, VINCENT HUY
• Application Number:
  US13/405,209
• Publication Number:
  US 20120185712A1
• Time in Patent Office: 487 Days
• Field of Search: 713/320, 713/322, 713/323, 713/324
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions.

Claims

1. A data processing system comprising:

a processing unit;

at least one bus coupled to the processing unit;

at least one subsystem coupled to the at least one bus;

a power controller coupled to the processing unit and to the at least one subsystem, the power controller being configured to reduce power consumed by the at least one subsystem in response to a first state of an instruction queue in memory for the at least one subsystem, the instruction queue being accessible to a software driver for the at least one subsystem which communicates a status of the first state to the processing unit which in response reduces power, through the power controller, to the at least one subsystem, wherein the first state represents an instruction queue having only instructions for future events or actions, and wherein, over a period of time, the power for the processing unit is reduced after a first period of time and the power for the subsystem is turned on such that it is on for a second period of time after the first period of time and then power to the processing unit is turned on to allow the processing unit to reduce power for the subsystem after the second period of time.

2. The data processing system of claim 1 wherein power to the at least one subsystem is reduced without using a timer to time a duration of non-use of the at least one subsystem, and wherein power is reduced by one of (a) turning power off completely;

(b) reducing an operating frequency of the at least one subsystem;

(c) reducing the operating frequency and an operating voltage of the at least one subsystem.

3. The data processing system of claim 1 wherein the at least one subsystem is at least one of (a) a data codec;

(b) a camera interface controller;

(c) a wireless interface controller;

(d) a controller for a dock;

(e) a serial bus interface controller;

(f) a digital signal processor; and

(g) a display controller.

4. The data processing system of claim 1 wherein the processing unit is a general purpose processing unit and wherein the power controller is further configured to reduce power for the general purpose processing unit in response to a state of an instruction queue of the general purpose processing unit.

5. The data processing system of claim 4 wherein power to the general purpose processing unit is reduced in response to determining that the instruction queue of the general purpose processing unit has only instructions for future events or actions.

6. A machine readable non-transitory storage medium containing executable program instructions which cause a data processing system to perform a method comprising:

determining a state of an instructions queue of a graphics processing unit;

turning off power to the graphics processing unit in response to determining that the instruction queue of the graphics processing unit (GPU) has instructions for only future events or actions;

determining a state of an instruction queue of a general purpose processing unit;

turning off power to the general purpose processing unit in response to determining that the instruction queue of the general purpose processing unit has instructions for only future events or actions, and wherein, over a period of time, the power for the general purpose processing unit is reduced after a first period of time and the power for the graphics processing unit (GPU) is turned on such that it is on for a second period of time after the first period of time and then power to the general purpose processing unit is turned on to allow the general purpose processing unit to reduce power for the GPU after the second period of time.

7. The non-transitory storage medium as in claim 6 wherein the graphics processing unit has its power turned off while an image, generated by the graphics processing unit, is being displayed by the data processing system.

8. The non-transitory storage medium as in claim 6 wherein the graphics processing unit has its power turned off between display frames.

9. The data processing system of claim 6 wherein the period of time is less than 60 seconds.

10. The non-transitory storage medium as in claim 6 wherein the general purpose processing unit (GPU) receives a maximum voltage, while operating at maximum frequency, when power is on for the GPU and receives about zero voltage when power is off for the GPU, and wherein the graphics processing unit (GPU) receives its maximum voltage, while operating its maximum frequency, when power is on for the GPU and receives about zero voltage when power is off for the GPU.

11. The non-transitory storage medium as in claim 6 wherein the general processing unit has its power turned off while an image, initiated by the processing of the general processing unit, is being displayed by the data processing system.

12. A data processing system on a monolithic semiconductor substrate which provides a system on a chip (SOC), the data processing system comprising:

a general purpose processing unit;

a graphics processing unit;

at least one peripheral interface controller;

at least one bus coupled to the general purpose processing unit, the graphics processing unit (GPU), and the at least one peripheral interface controller;

a power controller coupled to at least the general purpose processing unit and the graphics processing unit, the power controller being configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit, and the power controller being configured to turn power off for the graphics processing unit in response to a second state of an instruction queue of the graphics processing unit, and wherein over a period of time, the power for the general purpose processing unit is reduced after a first period of time and the power for the graphics processing unit (GPU) is turned on such that it is on for a second period of time after the first period of time and then power to the general purpose processing unit is turned on to allow the general purpose processing unit to reduce power for the GPU after the second period of time.

13. The data processing system as in claim 12 wherein the first state and the second state represent an instruction queue having instructions for only future events or actions.

14. The data processing system as in claim 12 wherein the graphics processing unit has its power turned off while an image, generated by the graphics processing unit, is being displayed by the data processing system.

15. The data processing system as in claim 12 wherein the graphics processing unit has its power turned off between display frames.

16. The data processing system of claim 12 wherein the period of time is less than 60 seconds.

17. The data processing system of claim 12 wherein the general purpose processing unit (GPU) receives a maximum voltage, while operating at maximum frequency, when power is on for the GPU and receives about zero voltage when power is off for the GPU, and wherein the graphics processing unit (GPU) receives its maximum voltage, while operating its maximum frequency, when power is on for the GPU and receives about zero voltage when power is off for the GPU.

18. The data processing system as in claim 12 wherein the general processing unit has its power turned off while an image, initiated by the processing of the general processing unit, is being displayed by the data processing system.