Optimizing power usage by processor cores based on architectural events

• US 8,473,766 B2
• Filed: 09/10/2012
• Issued: 06/25/2013
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Liu, Yen-Cheng, Or, P. Keong, Sistla, Krishnakanth, Srinivasa, Ganapati
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Application Number:
  US13/609,006
• Publication Number:
  US 20130031400A1
• Time in Patent Office: 288 Days
• Field of Search: 713/300, 713/320, 713/322, 713/323, 713/324, 713/600
• US Class Current: 713/323
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

Claims

1. A processor comprising:

eight processing cores;

one or more caches;

a power control unit;

a plurality of thermal sensors, wherein the plurality of thermal sensors are distributed within the processor to collect thermal data of the processor,

a plurality of event monitoring counters to monitor one or more events in the processor, wherein the one or more events include instructions retired per cycle, cache miss, stalls, and branch mis-prediction, and

a bus to couple the plurality of event monitoring counters and the plurality of thermal sensors to the power control unit, wherein the bus is to transfer data including the thermal data and the one or more events to the power control unit,

wherein the power control unit is to manage the power consumed by the processor based on the data received on the bus.