MLC self-RAID flash data protection scheme

• US 8,473,814 B2
• Filed: 06/27/2012
• Issued: 06/25/2013
• Est. Priority Date: 03/17/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Olbrich, Aaron K., Prins, Doug
• Primary Examiner(s): Wilson, Yolanda L
• Application Number:
  US13/535,250
• Publication Number:
  US 20120266032A1
• Time in Patent Office: 363 Days
• Field of Search: None
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.

Claims

1. A method of managing a multiple level cell flash memory that is organized logically into one or more blocks each having a plurality of pages, each page including a plurality of sectors, the multiple level cell flash memory further including sense circuitry, the method comprising:

detecting charge levels of a plurality of multiple level cells in the multiple level cell flash memory using a first sense voltage, and compiling a first correlation table of correlations between the first sense voltage and the detected charge levels of the plurality of multiple level cells;

selecting a second sense voltage that is lower than the first sense voltage and detecting charge levels of the plurality of multiple level cells using the second sense voltage, and compiling a second correlation table of correlations between the second sense voltage and the detected charge levels of the plurality of multiple level cells; and

replacing the first correlation table by the second correlation table.

2. The method of claim 1, further comprising:

programming and erasing data on a page at a predetermined speed;

detecting an error rate for each page of a block and identifying a group of high error pages based on the error rates; and

applying a speed slower than the predetermined speed in programming and erasing data on the identified high error pages.

3. The method of claim 2, further comprising:

(a) identifying a parity block;

(b) choosing a parity sector in each page of a respective block;

(c) assigning the pages of the respective block into a plurality of groups;

(d) for each page of the respective block, calculating a sector parity value for data stored in the sectors in the page and storing the sector parity value in the parity sector of the page;

(e) prior to completing data writing into all pages of a group in the respective block, calculating a subset group parity for a subset of pages in the group, the subset of pages comprising a plurality of pages in the group in the respective block; and

(f) storing the subset group parity in the parity block.

4. The method of claim 3, wherein the group in the respective block comprises a first group, and the method further comprises:

(g) repeating steps (e) to (f) for an additional subset of pages in a second group distinct from the first group.

5. The method as in claim 3, wherein the sectors of each page are each assigned a sector number, the method further comprising:

(h) selecting a column parity page and calculating, for each sector number, a column parity for all sectors assigned the sector number in the pages of the respective block.

6. The method as in claim 3, wherein each group consists of 8 pages.

7. The method as in claim 3, wherein each multiple level cell of a plurality of multiple level cells in the multiple level cell flash memory is shared by two pages of the same group.

8. The method as in claim 3, wherein the parity block resides outside the flash memory.

9. The method as in claim 3, wherein the parity block resides on a non-volatile memory.

10. The method as in claim 3, wherein the subset group parity, for the subset of pages in the respective group, is erased after data is completely written into the pages of the respective group.

11. The method as in claim 3, wherein the subset group parity, for the subset of pages in the respective group, is saved after data is completely written into the pages of the respective group.

12. The method as in claim 3, wherein the subset group parity, for the subset of pages in the respective group, is calculated from data in half of the pages of the respective group.

13. A flash memory data storage system operable in accordance with the method of claim 3.

14. The method of claim 2, further comprising:

(a) choosing a parity sector in each page of a respective block;

(b) assigning the pages of the respective block into a plurality of groups, each group in the respective block including an assigned parity page;

(c) for each page of the respective block, calculating a sector parity value for data stored in the sectors in the page and storing the sector parity value in the parity sector of the page;

(d) calculating a group parity value for data stored in the pages of the group; and

(e) storing the group parity value in the assigned parity page.

15. A multiple level cell flash memory data storage device, comprising:

a flash memory array having a plurality of blocks, each block in the plurality of blocks comprising an erase unit and having a plurality of pages, a respective block including a plurality of groups of pages, each group of pages in the respective block including an assigned parity page;

each page of the respective block having a plurality of sectors, including an assigned parity sector;

sense circuitry;

wherein the device is operable to;

detect charge levels of a plurality of multiple level cells in the multiple level cell flash memory using a first sense voltage, and compile a first correlation table of correlations between the first sense voltage and the detected charge levels of the plurality of multiple level cells;

select a second sense voltage that is lower than the first sense voltage and detect charge levels of the plurality of multiple level cells using the second sense voltage, and compile a second correlation table of correlations between the second sense voltage and the detected charge levels of the plurality of multiple level cells; and

replace the first correlation table by the second correlation table.

16. The multiple level cell flash memory data storage device of claim 15, wherein the device is further operable to:

program and erase data on a page at a predetermined speed;

detect an error rate for each page of a block and identify a group of high error pages based on the error rates; and

apply a speed slower than the predetermined speed in programming and erasing data on the identified high error pages.

17. The multiple level cell flash memory data storage device of claim 16,

wherein the device is further operable, for a respective page,

to store data in data sectors of the respective page;

to store, in the assigned parity sector of the respective page, a sector parity value of the data stored in the data sectors of the respective page; and

wherein the device is further operable, for a respective group of pages in the respective block,

to store data in data pages of the respective group of pages; and

to store, in a parity block, a subset group parity value calculated for a subset of pages in the respective group prior to completing data writing into all pages of the respective group.

18. The multiple level cell flash memory data storage device of claim 17, wherein the device is operable to calculate and store in the parity block a subset group parity value for multiple subsets of pages, each subset of pages in a distinct respective group.

19. The multiple level cell flash memory data storage device of claim 17, wherein the sectors of each page are each assigned a sector number, and the device is operable, for the respective group of pages, to select a column parity page for the respective block and to calculate, for each sector number, a column parity for all sectors assigned the sector number in the pages of the respective block.

20. The multiple level cell flash memory data storage device of claim 17, wherein each group consists of 8 pages.

21. The multiple level cell flash memory data storage device of claim 17, wherein the parity block resides outside the flash memory.

22. The multiple level cell flash memory data storage device of claim 17, wherein the parity block resides on a non-volatile memory.

23. The multiple level cell flash memory data storage device of claim 17, wherein the subset group parity, for the subset of pages in the respective group, is erased after data is completely written into the pages of the respective group.

24. The multiple level cell flash memory data storage device of claim 17, wherein the subset group parity, for the subset of pages in the respective group, is saved after data is completely written into the pages of the respective group.

25. The multiple level cell flash memory data storage device of claim 17, wherein the subset group parity, for the subset of pages in the respective group, is calculated from data in half of the pages of the respective group.

26. The multiple level cell flash memory data storage device of claim 17, wherein each multiple level cell of a plurality of multiple level cells in the multiple level cell flash memory is shared by two pages of the same group.

27. The multiple level cell flash memory data storage device of claim 17, wherein each multiple level cell of a plurality of multiple level cells in the multiple level cell flash memory is shared by two pages assigned to different groups.

28. The multiple level cell flash memory data storage device of claim 27, wherein the groups are each assigned a group number and wherein the pages sharing the respective multiple level cell are assigned consecutive group numbers.

29. The multiple level cell flash memory data storage device of claim 28, wherein one or more of the groups are assigned half the number of pages as assigned to each of the remainder of the groups of the respective block.

30. The multiple level cell flash memory data storage device of claim 16,

wherein the device is further operable, for a respective page,

to store data in data sectors of the respective page;

to store, in the assigned parity sector of the respective page, a sector parity value of the data stored in the data sectors of the respective page; and

wherein the device is further operable, for a respective group of pages in the respective block,

to store data in data pages of the respective group of pages; and

to store, in the parity page of the respective group, a group parity value of the data stored in the data pages of the respective group.