True bit level decoding of TTCM (turbo trellis coded modulation) of variable rates and signal constellations

• US 8,473,822 B2
• Filed: 11/30/2009
• Issued: 06/25/2013
• Est. Priority Date: 05/31/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shen, Ba-Zhong, Cameron, Kelly Brian, Tran, Hau Thien
• Primary Examiner(s): Baker, Stephen M
• Application Number:
  US12/627,438
• Publication Number:
  US 20100077282A1
• Time in Patent Office: 1,303 Days
• Field of Search: 714/780
• US Class Current: 714/780
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/258 with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H03M 13/2767 Interleaver wherein the permutation pattern or a portion thereof is stored
• CPC Class Codes: H03M 13/2771 Internal interleaver for turbo codes H03M13/2714 and H03M13/2725 take precedence
• CPC Class Codes: H03M 13/2785 Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/4123 implementing the return to a predetermined state
• CPC Class Codes: H03M 13/4161 implementing path management
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0055 MAP-decoding
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/0066 Parallel concatenated codes
• CPC Class Codes: H04L 1/0068 by puncturing
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis.

Claims

1. An apparatus, comprising:

a metric generator that is operative to process a plurality of symbols of a signal having information bits encoded therein thereby generating a plurality of symbol metrics;

a symbol metric decomposition module that is operative to decompose the plurality of symbol metrics to a plurality of bit metrics, such that each symbol metric of the plurality of symbol metrics is decomposed into a corresponding plurality of bit metrics;

a decoder module that is operative to process, on a bit level basis, the corresponding plurality of bit metrics thereby generating a corresponding plurality of extrinsic values, such that each extrinsic value of the plurality of extrinsic values corresponds to one respective bit metric of the plurality of bit metrics; and

a bit metric update module that is operative to update each bit metric of the plurality of bit metrics using a corresponding extrinsic value of the plurality of extrinsic values thereby generating a corresponding, updated plurality of bit metrics, such that each respective bit metric and corresponding extrinsic value corresponds to one respective bit of a plurality of bits within one respective symbol of the plurality of symbols; and

wherein;

the decoder module is operative to process, on a bit level basis, the corresponding, updated plurality of bit metrics thereby generating a corresponding, updated plurality of extrinsic values for use in making estimates of the information bits.

2. The apparatus of claim 1, wherein:

the plurality of bit metrics is a plurality of state dependent bit metrics; and

in accordance with generating the corresponding plurality of extrinsic values, the symbol metric decomposition module also is operative to convert the plurality of state dependent bit metrics to a plurality of state independent bit metrics.

3. The apparatus of claim 1, wherein:

the symbol metric decomposition module is operative to decompose;

a first symbol metric into a corresponding first plurality of bit metrics; and

a second symbol metric into a corresponding second plurality of bit metrics.

4. The apparatus of claim 1, wherein:

the decoder module is a first soft-in soft out decoder (SISO); and

further comprising;

a second SISO that is operative to process, on a bit level basis, the corresponding plurality of bit metrics thereby generating at least one additional corresponding plurality of extrinsic values; and

wherein;

the first SISO and the second SISO operate cooperatively to perform iterative decoding of the signal to make the estimates of the information bits.

5. The apparatus of claim 1, wherein:

the signal is a variable code rate signal, whose code rate varies on a symbol by symbol basis, such that each symbol of the plurality of symbols has a corresponding RC (Rate Control);

a first corresponding plurality of bit metrics, corresponding to a first symbol metric, are mapped to a first corresponding plurality of trellis metrics based on a first RC corresponding to a first symbol of the plurality of symbols; and

a second corresponding plurality of bit metrics, corresponding to a second symbol metric, are mapped to a second corresponding plurality of trellis metrics based on a second RC corresponding to a second symbol of the plurality of symbols.

6. The apparatus of claim 1, wherein:

the signal is a variable code rate signal whose code rate varies on a symbol by symbol basis;

a first symbol within the signal is encoded according to a first RC (Rate Control);

a second symbol within the signal is encoded according to a second RC;

the first RC includes a first modulation having a first constellation and a first mapping; and

the second RC includes a second modulation having a second constellation and a second mapping.

7. The apparatus of claim 1, further comprising:

a rate control sequencer that is coupled to each of the metric generator, the symbol metric decomposition module, and the decoder module; and

wherein;

the signal is a variable code rate signal, whose code rate varies on a symbol by symbol basis, such that each symbol of the plurality of symbols has a corresponding RC (Rate Control); and

each of the metric generator, the symbol metric decomposition module, and the decoder module operates adaptively based on a RC signal provided by the rate control sequencer.

8. The apparatus of claim 1, further comprising:

an interleaver/de-interleaver module, coupled to each of the decoder module and the bit metric update module, that is operative to interleave or de-interleave the corresponding plurality of extrinsic values before their use by the bit metric update module.

9. The apparatus of claim 1, wherein:

the decoder module is operative to make a respective soft bit decision for each of the information bits; and

further comprising;

an output processor that is operative to perform hard limiting of each respective soft bit decision thereby generating the estimates of the information bits.

10. The apparatus of claim 1, wherein:

the apparatus is a communication device that is operative to be implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.

11. An apparatus, comprising:

a metric generator that is operative to process a symbol of a signal having information bits encoded therein thereby generating a symbol metric;

a symbol metric decomposition module that is operative to decompose the symbol metric to a plurality of bit metrics, such that the plurality of symbol metrics includes a first bit metric corresponding to a first bit of the symbol and a second bit metric corresponding to a second bit of the symbol;

a decoder module that is operative to process the first bit metric and the second bit metric thereby generating a corresponding plurality of extrinsic values, such that the corresponding plurality of extrinsic values includes a first extrinsic value corresponding to the first bit of the symbol and a second extrinsic value corresponding to the second bit of the symbol; and

a bit metric update module that is operative to;

update the first bit metric using the first extrinsic value thereby generating an updated first bit metric; and

update the second bit metric using the second extrinsic value thereby generating an updated second bit metric; and

wherein;

the decoder module is operative to process the updated first bit metric and the updated second bit metric thereby generating a corresponding, updated plurality of extrinsic values, such that the corresponding, updated plurality of extrinsic values includes an updated first extrinsic value corresponding to the first bit of the symbol and an updated second extrinsic value corresponding to the second bit of the symbol; and

the updated first extrinsic value and the updated second extrinsic value are employed for use in making estimates of the information bits.

12. The apparatus of claim 11, wherein:

the signal is a variable code rate signal whose code rate varies on a symbol by symbol basis;

a first symbol within the signal is encoded according to a first RC (Rate Control);

a second symbol within the signal is encoded according to a second RC;

the first RC includes a first modulation having a first constellation and a first mapping; and

the second RC includes a second modulation having a second constellation and a second mapping.

13. The apparatus of claim 11, further comprising:

a rate control sequencer that is coupled to each of the metric generator, the symbol metric decomposition module, and the decoder module; and

wherein;

the signal is a variable code rate signal, whose code rate varies on a symbol by symbol basis, such that each symbol of the plurality of symbols has a corresponding RC (Rate Control); and

each of the metric generator, the symbol metric decomposition module, and the decoder module operates adaptively based on a RC signal provided by the rate control sequencer.

14. The apparatus of claim 11, further comprising:

an interleaver/de-interleaver module, coupled to each of the decoder module and the bit metric update module, that is operative to interleave or de-interleave the corresponding plurality of extrinsic values before their use by the bit metric update module.

15. The apparatus of claim 11, wherein:

the decoder module is operative to make a first soft bit decision for the first bit of the symbol and a second soft bit decision for the second bit of the symbol; and

further comprising;

an output processor that is operative to perform hard limiting of the first soft bit decision and the second soft bit decision in accordance with making the estimates of the information bits.

16. The apparatus of claim 11, wherein:

the apparatus is a communication device that is operative to be implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.

17. A method, comprising:

employing a metric generator to process a symbol of a signal having information bits encoded therein thereby generating a symbol metric;

decomposing the symbol metric to a plurality of bit metrics, such that the plurality of symbol metrics includes a first bit metric corresponding to a first bit of the symbol and a second bit metric corresponding to a second bit of the symbol;

employing a decoder to process the first bit metric and the second bit metric thereby generating a corresponding plurality of extrinsic values, such that the corresponding plurality of extrinsic values includes a first extrinsic value corresponding to the first bit of the symbol and a second extrinsic value corresponding to the second bit of the symbol;

updating the first bit metric using the first extrinsic value thereby generating an updated first bit metric;

updating the second bit metric using the second extrinsic value thereby generating an updated second bit metric; and

wherein;

processing the updated first bit metric and the updated second bit metric thereby generating a corresponding, updated plurality of extrinsic values, such that the corresponding, updated plurality of extrinsic values includes an updated first extrinsic value corresponding to the first bit of the symbol and an updated second extrinsic value corresponding to the second bit of the symbol; and

employing the updated first extrinsic value and the updated second extrinsic value for use in making estimates of the information bits.

18. The method of claim 17, wherein:

the signal is a variable code rate signal, whose code rate varies on a symbol by symbol basis, such that each symbol of the plurality of symbols has a corresponding RC (Rate Control);

a first corresponding plurality of bit metrics, corresponding to a first symbol metric, are mapped to a first corresponding plurality of trellis metrics based on a first RC corresponding to a first symbol of the plurality of symbols; and

a second corresponding plurality of bit metrics, corresponding to a second symbol metric, are mapped to a second corresponding plurality of trellis metrics based on a second RC corresponding to a second symbol of the plurality of symbols.

19. The method of claim 17, further comprising:

making a first soft bit decision for the first bit of the symbol;

making a second soft bit decision for the second bit of the symbol; and

performing hard limiting of the first soft bit decision and the second soft bit decision in accordance with making the estimates of the information bits.

20. The method of claim 17, wherein:

the method is performed within a communication device that is operative to be implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.