Method for synchronizing independent cooperative thread arrays running on a graphics processing unit

• US 8,473,948 B1
• Filed: 08/08/2007
• Issued: 06/25/2013
• Est. Priority Date: 08/08/2007
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Le Grand, Scott M.
• Primary Examiner(s): Puente, Emerson
• Assistant Examiner(s): Labud, Jonathan R
• Application Number:
  US11/836,017
• Time in Patent Office: 2,148 Days
• Field of Search: None
• US Class Current: 718/100
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

One embodiment of the present invention sets forth a technique for synchronizing the execution of multiple cooperative thread arrays (CTAs) implementing a parallel algorithm that is mapped onto a graphics processing unit. An array of semaphores provides synchronization status to each CTA, while one designated thread within each CTA provides updated status for the CTA. The designated thread within each participating CTA reports completion of a given computational phase by updating a current semaphore within the array of semaphores. The designated thread then polls the status of the current semaphore until all participating CTAs have reported completion of the current computational phase. After each CTA has completed the current computational phase, all participating CTAs may proceed to the next computational phase.

Claims

1. A method for synchronizing a plurality of cooperative thread arrays (CTAs) executing an algorithm within a parallel processing system, the method comprising:

for a first plurality of threads within each CTA of the plurality of CTAs, performing a first set of computations associated with a first pass of the algorithm;

for each CTA in the plurality of CTAs, performing a thread synchronization operation across the first plurality of threads with the CTA to ensure that all threads within the first plurality of threads within the CTA have completed the first set of computations;

for each CTA in the plurality of CTAs, performing an atomic add operation via a first thread within the CTA to increment a first semaphore to indicate that all threads within the first plurality of threads within the CTA have completed the first set of computations; and

for each CTA in the plurality of CTAs, performing a semaphore wait operation to ensure that each CTA within the plurality of CTAs has completed the first set of computations.

2. The method of claim 1, further comprising, for each CTA in the plurality of CTAs, polling the first semaphore to determine whether each CTA within the plurality of CTAs has completed the first set of computations.

3. The method of claim 2, wherein each CTA within the plurality of CTAs have completed the first set of computations when the value of the first semaphore equals the number of CTAs in the plurality of CTAs.

4. The method of claim 2, further comprising the step of, for a CTA within the plurality of CTAs, performing a zero semaphore operation to clear a second semaphore for a second set of computations associated with the algorithm.

5. The method of claim 4, wherein the second semaphore is two increments ahead of the first semaphore in a semaphore index.

6. The method of claim 2, further comprising the step of, for each CTA in the plurality of CTAs, incrementing a semaphore index to make a second semaphore available for a second set of computations associated with the algorithm.

7. The method of claim 6, further comprising the step of, for each CTA in the plurality of CTAs, performing a thread synchronization operation across a second plurality of threads within the CTA.

8. The method of claim 7, further comprising the step of, for the second plurality of threads within each CTA, performing the second set of computations.

9. A non-transitory computer-readable medium including instructions that, when executed by a processing unit, cause the processing unit to synchronize a plurality of cooperative thread arrays (CTAs) executing an algorithm, by performing the steps of:

for a first plurality of threads within each CTA of the plurality of CTAs, performing a first set of computations associated with a first pass of the algorithm;

for each CTA in the plurality of CTAs, performing a thread synchronization operation across the first plurality of threads of each CTA to ensure that all threads within the first plurality of threads within the CTA have completed the first set of computations;

for each CTA in the plurality of CTAs, performing an atomic add operation via a first thread within the CTA to increment a first semaphore to indicate that all threads within the first plurality of threads within the CTA have completed the first set of computations; and

for each CTA in the plurality of CTAs, performing a semaphore wait operation to ensure that each CTA within the plurality of CTAs has completed the first set of computations.

10. The computer-readable medium of claim 9, further comprising, for each CTA in the plurality of CTAs, polling the first semaphore to determine whether each CTA within the plurality of CTAs has completed the first set of computations.

11. The computer-readable medium of claim 10, further comprising the step of, for a CTA within the plurality of CTAs, performing a zero semaphore operation to clear a second semaphore for a second set of computations associated with the algorithm.

12. The computer-readable medium of claim 10, further comprising the step of, for each CTA in the plurality of CTAs, incrementing a semaphore index to make a second semaphore available for a second set of computations associated with the algorithm.

13. The computer-readable medium of claim 12, further comprising the step of, for each CTA in the plurality of CTAs, performing a thread synchronization operation across a second plurality of threads within the CTA.

14. The computer-readable medium of claim 13, further comprising the step of, for the second plurality of threads within each CTA, performing the second set of computations.

15. A computing device configured to synchronize a plurality of cooperative thread arrays (CTAs) executing an algorithm, the computing device comprising:

a memory; and

a parallel processing unit coupled to the memory, wherein the plurality of CTAs executes within the parallel processing unit, and the plurality of CTAs is configured such that;

a first plurality of threads within each CTA of the plurality of CTAs performs a first set of computations associated with a first pass of the algorithm,

each CTA performs a thread synchronization operation across the first plurality of threads to ensure that all threads within the first plurality of threads within the CTA have completed the first set of computations,

a first thread within each CTA performs an atomic add operation to increment a first semaphore to indicate that all threads within the first plurality of threads within the CTA have completed the first set of computations, and

each CTA in the plurality of CTAs performs a semaphore wait operation to ensure that each CTA within the plurality of CTAs has completed the first set of computations.

16. The computing device of claim 15, wherein the plurality of CTAs is further configured such that each CTA in the plurality of CTAs polls the first semaphore to determine whether each CTA has completed the first set of computations.

17. The computing device of claim 16, wherein the plurality of CTAs is further configured such that a CTA within the plurality of CTAs performs a zero semaphore operation to clear a second semaphore for a second set of computations associated with the algorithm.

18. The computing device of claim 16, wherein the plurality of CTAs is further configured such that each CTA in the plurality of CTAs increments a semaphore index to make a second semaphore available for a second set of computations associated with the algorithm.

19. The computing device of claim 18, wherein the plurality of CTAs is further configured such that each CTA in the plurality of CTAs performs a thread synchronization operation across a second plurality of threads within the CTA.

20. The computing device of claim 19, wherein the plurality of CTAs is further configured such that the second plurality of threads within each CTA performs the second set of computations.