Computer or microchip with a master controller connected by a secure control bus to networked microprocessors or cores
First Claim
1. A computer or microchip configured to be securely controlled through a private network, said computer or microchip comprising:
- at least a secure private unit of said computer or microchip that is protected by an inner hardware-based access barrier or firewall;
an unprotected public unit of said computer or microchip, said unprotected public unit including at least one network connection configured to connect to a network of computers including the Internet;
at least a separate private network connection configured for connection to at least said private network of computers, at least said separate private network connection being located in at least said secure private unit of said computer or microchip;
at least one microprocessor, core or processing unit configured for general purposes is located in said unprotected public unit, wherein said at least one microprocessor, core or processing unit is separate from said inner hardware-based access barrier or firewall;
at least a master controlling device for the computer or microchip located in said secure private unit; and
a secure control bus configured to connect at least said master controlling device with at least said microprocessor, core or processing unit located in said unprotected public unit, said secure control bus being isolated from input from said network and input from components of said unprotected public unit; and
said master controlling device being configured for securely controlling at least one operation executed by at least one said microprocessor, core or processing unit in said unprotected public unit, said secure control being provided by said master controlling device in said secure private unit through said separate private network to said additional and separate private network connection in said secure private unit and via said secure control bus.
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Accused Products
Abstract
A computer or microchip configured to be securely controlled through a secure control bus, including through a private network. The computer or microchip includes a secure private unit protected by an inner hardware-based access barrier or firewall; an unprotected public unit including at least one network connection configured to connect to a network; a separate private network connection located in the secure private unit; a microprocessor, core or processing unit configured for general purposes located in the unprotected public unit and separate from the access barrier or firewall; a secure control bus isolated from input from both the network and components of the unprotected public unit; and a master controlling device in the private unit being configured for securely controlling an operation executed by the microprocessor, core or processing unit via a connection to the secure control bus, including through the separate private network to the separate private network connection.
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Citations
49 Claims
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1. A computer or microchip configured to be securely controlled through a private network, said computer or microchip comprising:
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at least a secure private unit of said computer or microchip that is protected by an inner hardware-based access barrier or firewall; an unprotected public unit of said computer or microchip, said unprotected public unit including at least one network connection configured to connect to a network of computers including the Internet; at least a separate private network connection configured for connection to at least said private network of computers, at least said separate private network connection being located in at least said secure private unit of said computer or microchip; at least one microprocessor, core or processing unit configured for general purposes is located in said unprotected public unit, wherein said at least one microprocessor, core or processing unit is separate from said inner hardware-based access barrier or firewall; at least a master controlling device for the computer or microchip located in said secure private unit; and a secure control bus configured to connect at least said master controlling device with at least said microprocessor, core or processing unit located in said unprotected public unit, said secure control bus being isolated from input from said network and input from components of said unprotected public unit; and said master controlling device being configured for securely controlling at least one operation executed by at least one said microprocessor, core or processing unit in said unprotected public unit, said secure control being provided by said master controlling device in said secure private unit through said separate private network to said additional and separate private network connection in said secure private unit and via said secure control bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A computer or microchip configured to be securely controlled, said computer or microchip comprising:
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an inner hardware-based access barrier or firewall communicatively connected to a secure private unit of said computer or microchip that is protected by said inner hardware-based access barrier or firewall, said inner hardware-based access barrier or firewall being located between said secure private unit and an unprotected public unit of said computer or microchip, and said unprotected public unit being configured to connect to a network of computers including the Internet; at least one microprocessor, core or processing unit located in said unprotected public unit, wherein said at least one microprocessor, core or processing unit is configured for general purposes and is separate from said inner hardware-based access barrier or firewall; at least a master controlling device for the computer or microchip located in said secure private unit; and a secure control bus configured to connect at least said master controlling device with at least said at least one microprocessor, core or processing unit located in said unprotected public unit, and said secure control bus being isolated from input from said network and input from components of said unprotected public unit; and said master controlling device being configured for securely controlling at least one operation executed by at least one said microprocessor, core or processing unit in said unprotected public unit, said secure control being provided by said master controlling device in said secure private unit via said secure control bus. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A computer or microchip configured to be securely controlled, said computer or microchip comprising:
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at least a first secure private unit of said computer or microchip that is protected by at least a first inner hardware-based access barrier or firewall; an unprotected public unit of said computer or microchip, said unprotected public unit being configured to connect to a network of computers including the Internet; at least a second secure private unit that is protected by at least a second hardware-based access barrier or firewall, said second secure private unit including at least one computer or microchip component; at least one microprocessor, core or processing unit configured for general purposes is located in said unprotected public unit, wherein said at least one microprocessor, core or processing unit is separate from said inner hardware-based access barrier or firewall; at least a master controlling device for the computer or microchip located in at least said first secure private unit; and a secure control bus configured to connect at least said master controlling device with at least said microprocessor, core or processing unit located in said unprotected public unit and said at least one component in said second secure private unit, and said secure control bus being isolated from input from said network and input from components of said unprotected public unit; and said master controlling device being configured for securely controlling at least one operation executed by at least one said microprocessor, core or processing unit in said unprotected public unit and said at least one component in said second secure private unit, said secure control being provided by said master controlling device in said first secure private unit via said secure control bus. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. A computer or microchip configured to be securely controlled, said computer or microchip comprising:
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at least one microprocessor, core or processing unit being configured for general purposes and configured to connect to a network of computers including the Internet; at least a master controlling device for the computer or microchip; and a secure control bus configured to connect at least said master controlling device with at least said at least one microprocessor, core or processing unit, and said secure control bus being isolated from input from said network and input from components of said computer or microchip other than said master controlling device; and said master controlling device being configured for securely controlling at least one operation executed by at least one said microprocessor, core or processing unit, said secure control being provided by said master controlling device via said secure control bus. - View Dependent Claims (41, 42, 43, 44)
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45. A computer or microchip configured to be securely controlled through a private network, said computer or microchip comprising:
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at least one network connection to a network of computers including the Internet; at least a separate private network connection configured for connection to at least a private network of computers, at least said separate private network connection being located in a hardware protected area of said computer or microchip, at least one microprocessor, core or processing unit configured for general purposes and configured to connect to said at least one connection to a network of computers including the Internet; at least a master controlling device for the computer or microchip located in said hardware protected area; and a secure control bus configured to connect at least said master controlling device with at least said microprocessor, core or processing unit, said secure control bus being isolated from input from said network and input from components of said computer or microchip other than said master controlling device; and said master controlling device being configured for securely controlling at least one operation executed by at least one said microprocessor, core or processing unit, said secure control being provided by said master controlling device through said separate private network to said additional and separate private network connection in said hardware protected area and through said secure control bus. - View Dependent Claims (46, 47, 48, 49)
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Specification