Method and structure of sensors or electronic devices using vertical mounting

• US 8,476,084 B1
• Filed: 05/23/2011
• Issued: 07/02/2013
• Est. Priority Date: 05/24/2010
• Status: Active Grant

• Current Assignee: Movella Incorporated (Movella Holdings, Inc.)
• Original Assignee: mCube, Inc.
• Inventors: Yang, Xiao Charles, Wan, Hong
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US13/113,883
• Time in Patent Office: 771 Days
• Field of Search: 438/51, 438/114, 438/617
• US Class Current: 438/3
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81B 7/0074 3D packaging, i.e. encapsulation containing one or several MEMS devices arranged in planes non-parallel to the mounting board
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/4847 the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10156 : at the periphery
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

A method and structure for fabricating sensor(s) or electronic device(s) using vertical mounting is presented. The method includes providing a substrate having a surface region and forming sensor(s) or electronic device(s) on a first region overlying the surface region. At least one bond pad structure can be formed from at least one trench structure. The resulting device can then be singulated within a vicinity of the bond pad structure(s) to form at least one integrated sensor or electronic devices having at least one vertical bond pad. At least one singulated device(s) can be coupled to a package, having a package surface region, such that the vertical bond pad(s) are configured horizontally, and at least one interconnection can be formed between the vertical bond pad(s) and at least one portion of the package surface region.

Claims

1. A method for fabricating an integrated device, the method comprising:

providing a substrate having a surface region;

forming at least one integrated device provided on a first region overlying the surface region, the at least one integrated device having at least one contact region, the first region having a first surface region, the at least one integrated device including one or more sensors and/or one or more electronic devices;

forming at least one trench structure within at least one portion of the first region;

forming a dielectric material overlying the first region and the at least one trench structure;

removing at least one portion of the dielectric material within a vicinity of the at least one contact region;

forming a conduction material overlying the dielectric material, the at least one trench structure, and the at least one contact region;

removing at least one portion of the conduction material within a vicinity of the at least one contact region and the at least one trench structure to form at least one bonding structure;

singulating the resulting device within a vicinity of the at least one bonding structure to form at least one singulated integrated device having at least one vertical bond pad;

coupling the at least one singulated integrated device to a package, the package having a package surface region, the at least one singulated device being coupled to the package surface region such that the at least one vertical bond pad is configured horizontally; and

forming at least one interconnection between the at least one vertical bond pad and at least a portion of the package surface region.

2. The method of claim 1 wherein the at least one integrated device comprises a nickel-iron material.

3. The method of claim 1 wherein the electronic devices comprise CMOS integrated circuit devices.

4. The method of claim 1 wherein the sensors comprise MEMS devices.

5. The method of claim 1 wherein the sensors comprise magnetoresistance devices.

6. The method of claim 5 wherein the magnetoresistance devices comprise anisotropic magnetoresistance (AMR), ordinary magnetoresistance (OMR), giant magnetoresistance (GMR), or tunnel junction magneto resistance (TMR) devices.

7. The method of claim 1 wherein the at least one trench structure is formed from a wet etching, dry etching, deep reactive-ion etching (DRIE), or mechanical process.

8. The method of claim 1 wherein the removing of at least one portion of the dielectric material and the removing of at least one portion of the conduction material comprise a wet etching, dry etching, or mechanical process.

9. The method of claim 1 wherein the singulating of the resulting device comprises a dicing, an etching, or a laser scribing process.

10. The method of claim 1 wherein the package is a substrate package or a lead frame package.

11. The method of claim 1 wherein the at least one interconnection is formed via a wire bonding process.

12. A method for fabricating an integrated device, the method comprising:

providing a substrate having a surface region;

forming at least one integrated device provided on a first region overlying the surface region, the at least one integrated device having at least one contact region, the first region having a first surface region, the at least one integrated device including one or more sensors and/or one or more electronic devices;

forming at least one trench structure within at least one portion of the first region, the at least one trench structure being formed via a deep reactive-ion etching (DRIE) process, the trench sidewalls having slopes greater than 90 degrees;

forming a dielectric material overlying the first region and the at least one trench structure;

removing at least one portion of the dielectric material within a vicinity of the at least one contact region;

forming a conduction material overlying the dielectric material, the at least one trench structure, and the at least one contact region;

removing at least one portion of the conduction material within a vicinity of the at least one contact region and the at least one trench structure to form at least one bonding structure;

singulating the resulting device within a vicinity of the at least one bonding structure to form at least one singulated integrated device having at least one vertical bond pad;

coupling the at least one singulated integrated device to a package, the package having a package surface region, the at least one singulated device being rotated 90 degrees and being coupled to the package surface region such that the at least one vertical bond pad is configured horizontally;

forming at least one interconnection between the at least one vertical bond pad and at least a portion of the package surface region; and

forming an encapsulation overlying the at least one singulated integrated device, the at least one interconnection, and the package.

13. The method of claim 12 wherein the at least one integrated device comprises a nickel-iron material.

14. The method of claim 12 wherein the electronic devices comprise CMOS integrated circuit devices.

15. The method of claim 12 wherein the sensors comprise MEMS devices.

16. The method of claim 12 wherein the sensors comprise magnetoresistance devices.

17. The method of claim 16 wherein the magnetoresistance devices comprise anisotropic magnetoresistance (AMR), ordinary magnetoresistance (OMR), giant magnetoresistance (GMR), or tunnel junction magnetoresistance (TMR) devices.

18. The method of claim 12 wherein the at least one trench structure is formed from a wet etching, dry etching, deep reactive-ion etching (DRIE), or mechanical process.

19. The method of claim 12 wherein the removing of at least one portion of the dielectric material and the removing of at least one portion of the conduction material comprise a wet etching, dry etching, or mechanical process.

20. The method of claim 12 wherein the singulating of the resulting device comprises a dicing, an etching, or a laser scribing process.

21. The method of claim 12 wherein the package is a substrate package or a lead frame package.

22. The method of claim 12 wherein the at least one interconnection is formed via a wire bonding process.