Reduction of etch microloading for through silicon vias

• US 8,476,116 B2
• Filed: 10/31/2012
• Issued: 07/02/2013
• Est. Priority Date: 07/08/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Hung-Pin, Yu, Chen-Hua
• Primary Examiner(s): Le, Thao P.
• Application Number:
  US13/665,164
• Publication Number:
  US 20130059443A1
• Time in Patent Office: 244 Days
• Field of Search: 438/122, 257/E23.101
• US Class Current: 438/122
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48229 the bond pad protruding from the surface of the item
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2933/0075 : relating to heat extraction or cooling elements
• CPC Class Codes: H01L 33/642 : characterized by the shape
• CPC Class Codes: H01L 33/647 : the elements conducting electric current to or from the semiconductor body

Abstract

A method of making a support structure is provided. The method includes depositing a photoresist layer on a substrate of the support structure and patterning the photoresist layer. The method further includes etching the patterned photoresist layer. Etching the patterned photoresist includes forming a first group of through silicon vias (TSVs) configured to electrically connect a first surface of the substrate to a first electrical interface adjacent an opposite second surface of the substrate. Etching the patterned photoresist further includes forming a second group of TSVs configured to conduct thermal energy from the first surface of the substrate to a thermal interface adjacent the second surface of the substrate. A difference in cross-sectional area between TSVs in the first group of TSVs and TSVs in the second group of TSVs is less than 10%, and the first electrical interface is separated from the thermal interface.

Claims

1. A method of making a support structure, the method comprising:

depositing a photoresist layer on a substrate of the support structure;

patterning the photoresist layer;

etching the patterned photoresist layer, wherein etching the patterned photoresist comprises;

forming a first group of through silicon vias (TSVs) configured to electrically connect a first surface of the substrate to a first electrical interface adjacent an opposite second surface of the substrate; and

forming a second group of TSVs configured to conduct thermal energy from the first surface of the substrate to a thermal interface adjacent the second surface of the substrate,

wherein a difference in cross-sectional area between TSVs in the first group of TSVs and TSVs in the second group of TSVs is less than 10%, and the first electrical interface is separated from the thermal interface.

2. The method of claim 1, wherein the second group of TSVs are further configured to electrically connect the first surface of the substrate to a second electrical interface, and the second electrical interface is the same as the thermal interface.

3. The method of claim 1, wherein etching the patterned photoresist layer further comprises:

forming a third group of TSVs configured to electrically connect the first surface of the substrate to a second electrical interface, wherein the second electrical interface is separated from the first electrical interface and the thermal interface.

4. The method of claim 1, further comprising depositing a dielectric layer on the substrate between the photoresist layer and the substrate.

5. The method of claim 1, further comprising depositing a lining dielectric layer in the first group of TSVs and the second group of TSVs.

6. The method of claim 1, further comprising simultaneously forming the first group of TSVs and the second group of TSVs.

7. The method of claim 1, wherein forming the first group of TSVs comprises forming the first group of TSVs having a first aspect ratio ranging from 3 to 10, and forming the second group of TSVs comprises forming the second group of TSVs having a second aspect ratio equal to the first aspect ratio.

8. The method of claim 1, wherein forming the second group of TSVs comprises forming a greater number of TSVs than forming the first group of TSVs.

9. The method of claim 1, wherein forming the first group of TSVs comprises forming the first group of TSVs having a first pattern density, forming the second group of TSVs comprises forming the second group of TSVs having a second pattern density, and a difference between the first pattern density and the second pattern density ranges from 0% to 10%.

10. The method of claim 1, wherein forming the first group of TSVs comprises forming the first group of TSVs having a first depth ranging from 20 microns (μ

m) to 300 μ

m, and forming the second group of TSVs comprises forming the second group of TSVs having a second depth equal to the first depth.

11. The method of claim 1, wherein forming the first group of TSVs comprises forming the first group of TSVs having a first diameter ranging from 5 microns (μ

m) to 50 μ

m, and forming the second group of TSVs comprises forming the second group of TSVs having a second diameter equal to the first diameter.

12. A method of making a support structure, the method comprising:

depositing a photoresist layer on a substrate of the support structure;

patterning the photoresist layer;

etching the patterned photoresist layer, wherein etching the patterned photoresist comprises;

forming a first group of through silicon vias (TSVs) configured to electrically connect a first surface of the substrate to a first electrical interface adjacent an opposite second surface of the substrate;

forming a second group of TSVs configured to conduct thermal energy from the first surface of the substrate to a thermal interface adjacent the second surface of the substrate; and

forming a third group of TSVs configured to electrically connect the first surface of the substrate to a second electrical interface adjacent an opposite second surface of the substrate,

wherein the first electrical interface is separate from the thermal interface and the second electrical interface, and

the TSVs of the first group of TSVs, the TSVs of the second group of TSVs, and the TSVs of the third group of TSVs have a same depth and diameter.

13. A method of preparing for a support structure of a light-emitting device (LED) chip, comprising:

preparing a photomask for patterning through silicon vias (TSVs), wherein the TSVs are divided into at least a first group and a second group, and wherein the first group of TSVs provides electrical connection for the LED chip and the second group of TSVs provides a function of heat dissipation for the LED chip;

wherein the first group of TSVs are arranged in a first pattern with a first pattern density and the second group of TSVs are arranged in a second pattern with a second pattern density, and wherein a difference between the first pattern density and the second pattern density has an absolute value between about 0.1% to about 5%;

depositing a photoresist layer on a substrate for the support structure;

patterning the deposited photoresist layer on the substrate by using the prepared photomask; and

etching the substrate by using a deep reactive ion etching process for silicon after the deposited photoresist layer is patterned.

14. The method of claim 13, further comprising:

depositing a sacrificial dielectric layer on the substrate before depositing the photoresist layer.

15. The method of claim 13, wherein the deep reactive ion etching process for silicon uses SF₆ as a reactive gas.

16. The method of claim 13, wherein etch depth of the TSVs is between about 30 μ

m to about 400 μ

m.

17. The method of claim 13, wherein the photoresist layer is a dry film resist.

18. The method of claim 13, wherein the first group of TSVs and the second group of TSVs each has significantly same shapes, significantly same sizes, and significantly same aspect ratios.

19. The method of claim 13, wherein the difference between the first pattern density and the second pattern density reduces a microloading effect.

20. The method of claim 13, wherein the first pattern density is greater than the second pattern density.