Method and a structure for enhancing electrical insulation and dynamic performance of MIS structures comprising vertical field plates

• US 8,476,136 B2
• Filed: 12/13/2011
• Issued: 07/02/2013
• Est. Priority Date: 12/14/2010
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Borzi, Anna, Coccorese, Corrado, Morale, Giuseppe, Repici, Domenico
• Primary Examiner(s): Roman, Angel
• Application Number:
  US13/324,896
• Publication Number:
  US 20120146135A1
• Time in Patent Office: 567 Days
• Field of Search: 438/270, 438/589, 257/296, 257/328, 257/330, 257/E21.19, 257/E29.262
• US Class Current: 438/270
• CPC Class Codes: H01L 21/31658 by thermal oxidation, e.g. of SiGe
• CPC Class Codes: H01L 21/32105 Oxidation of silicon-containing layers
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In an MIS structure a field plate electrode is incorporated below a buried gate electrode by using an insulating oxide layer, which is formed concurrently with the gate dielectric layer. In order to obtain superior dynamic behavior and enhanced dielectric strength the oxidation behavior of the field plate electrode is modified, for instance by incorporating a desired high concentration of arsenic.

Claims

1. A method of forming an MIS (metal-insulator-semiconductor) structure, the method comprising:

forming a first semiconductor electrode in a cavity formed in a crystalline semiconductor region, said first semiconductor electrode being electrically insulated from said crystalline semiconductor region by an insulating layer, wherein forming the first semiconductor electrode includes forming a first semiconductor layer that includes a first added species and forming a second semiconductor layer that includes a second added species, the first semiconductor layer being positioned between the second semiconductor layer and the insulating layer, wherein the second added species is configured to increase an oxidation rate of at least a portion of a surface of said first semiconductor electrode relatively to an exposed surface of said crystalline semiconductor region in said cavity,

forming a first oxide layer on said exposed surface of said first semiconductor electrode and a second oxide layer on said exposed surface of said crystalline semiconductor region by concurrently oxidizing said exposed surface of said crystalline semiconductor region in said cavity and the exposed surface of said first semiconductor electrode, and

forming a second semiconductor electrode in said cavity and above said first semiconductor electrode, said second semiconductor electrode being electrically insulated from said first semiconductor electrode by said first oxide layer.

2. The method of claim 1, wherein the second added species includes an arsenic dopant species.

3. The method of claim 2, wherein said arsenic dopant species is at least partially incorporated while depositing the semiconductor layer.

4. The method of claim 1, wherein forming the first semiconductor layer comprises forming a first silicon containing layer in said cavity and in-situ doping said first silicon containing layer with said first added species.

5. The method of claim 4, wherein forming the second semiconductor layer comprises depositing a second silicon containing layer above said first silicon containing layer and adding the second added species to said second silicon containing layer.

6. The method of claim 1, wherein said second added species is at least partially incorporated by performing an ion implantation process.

7. The method of claim 1, wherein forming said second semiconductor layer comprises inducing crystal damage in a part of said second semiconductor layer by performing an ion implantation process using a non-doping implantation species as the second added species.

8. The method of claim 7, wherein said non-doping implantation species comprises one of silicon, germanium, xenon and argon.

9. The method of claim 1, wherein forming said first semiconductor layer comprises forming a semiconductor alloy.

10. The method of claim 9, wherein said semiconductor alloy comprises germanium.

11. An MIS (metal-insulator-semiconductor) structure comprising:

a crystalline semiconductor region having a cavity,

a first insulation layer in the cavity,

a first semiconductor electrode formed in said cavity and electrically insulated from sidewalls of said cavity by the first insulation layer, said first semiconductor electrode including;

a first semiconductor layer that includes a first oxidation rate increasing species configured to increase an oxidation rate of the first semiconductor layer, and

a second semiconductor layer, the first semiconductor layer being positioned between the second semiconductor layer and the insulating layer,

a second semiconductor electrode formed in a part of said cavity above said first semiconductor electrode,

a second insulation layer formed between said first and second semiconductor electrodes, said second insulation layer having a first average thickness and comprising a second oxidation rate increasing species, and

a third insulation layer formed between said second semiconductor electrode and said sidewalls of said cavity, said third insulation layer having a second average thickness that is less than said first average thickness.

12. The MIS structure of claim 11, wherein said first and second semiconductor electrodes comprise silicon and wherein said first oxidation rate increasing species is arsenic.

13. The MIS structure of claim 11, wherein said second oxidation rate increasing species is also incorporated in an upper portion of said second semiconductor layer.

14. The MIS structure of claim 13, wherein the first oxidation rate increasing species is a dopant species and the second oxidation rate increasing species is a non-dopant species.

15. The MIS structure of claim 11, wherein said MIS structure is a vertical transistor structure with said second semiconductor electrode being a gate electrode of the vertical transistor structure.

16. A method of forming an MIS (metal-insulator-semiconductor) structure, the method comprising:

forming a first semiconductor electrode in a cavity formed in a crystalline semiconductor region, said first semiconductor electrode being electrically insulated from said crystalline semiconductor region by an insulating layer;

forming a first oxide layer on an exposed surface of said first semiconductor electrode in said cavity and a second oxide layer on an exposed surface of said crystalline semiconductor region by concurrently oxidizing the exposed surface of said crystalline semiconductor region and the exposed surface of said first semiconductor electrode; and

forming a second semiconductor electrode in said cavity and above said first semiconductor electrode, said second semiconductor electrode being electrically insulated from said first semiconductor electrode by said first oxide layer, wherein forming said first semiconductor electrode comprises depositing a first silicon containing layer with an increased oxidation rate relative to the exposed surface of said crystalline semiconductor region in said cavity and depositing a second silicon containing layer above said first silicon containing layer with a different oxidation rate relative to said first silicon containing layer.

17. The method of claim 16, wherein forming the first silicon containing layer includes incorporating an arsenic dopant species in the first silicon containing layer.

18. The method of claim 16, wherein forming the first silicon containing layer relative to the exposed surface of said crystalline semiconductor region in said cavity comprises forming the first silicon containing layer as a semiconductor alloy.

19. The method of claim 18, wherein said semiconductor alloy comprises germanium.

20. The method of claim 16, wherein forming said first semiconductor electrode includes increasing the oxidation rate of the exposed surface the first semiconductor electrode relative to the exposed surface of said crystalline semiconductor region in said cavity by performing an ion implantation process.

21. The method of claim 20, wherein performing the ion implantation process includes using a non-doping implantation species to induce crystal damage in the exposed surface of said first semiconductor electrode.

22. The method of claim 21, wherein said non-doping implantation species comprises one of silicon, germanium, xenon and argon.

23. An MIS (metal-insulator-semiconductor) structure comprising:

a crystalline semiconductor region having a cavity;

a first semiconductor electrode formed in said cavity and electrically insulated from sidewalls of said cavity, said first semiconductor electrode having an upper semiconductor portion;

a second semiconductor electrode positioned in a part of said cavity above said upper semiconductor portion of said first semiconductor electrode;

a first insulation layer positioned between said first and second semiconductor electrodes, said first insulation layer having a first average thickness; and

a second insulation layer positioned between said second semiconductor electrode and said sidewalls of said cavity, said second insulation layer having a second average thickness that is less than said first average thickness, wherein;

said first semiconductor electrode comprises an atomic species that imparts an increased oxidation rate relative to an exposed surface of said crystalline semiconductor region in said cavity; and

said atomic species is locally restricted to a surface layer in said first semiconductor electrode.

24. The MIS structure of claim 23, wherein said first semiconductor electrode comprise silicon and wherein said atomic species is arsenic.

25. The MIS structure of claim 23, wherein said first semiconductor electrode comprise silicon and wherein said atomic species is non-doping implantation species.

26. The MIS structure of claim 25, wherein said non-doping implantation species comprises one of germanium, xenon and argon.

27. The MIS structure of claim 23, wherein said MIS structure is a vertical transistor structure with said second semiconductor electrode being a gate electrode.