Device using oxide semiconductor, display device, and electronic apparatus

• US 8,476,628 B2
• Filed: 10/17/2011
• Issued: 07/02/2013
• Est. Priority Date: 12/13/2010
• Status: Active Grant

• Current Assignee: JDI Design and Development GK
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Minami, Tetsuo, Uchino, Katsuhide
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US13/317,373
• Publication Number:
  US 20120146036A1
• Time in Patent Office: 624 Days
• Field of Search: 257/43, 257/59, 257/E29.389, 257/E29.296, 345/48, 345/55, 345/76, 345/204
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence

Abstract

Disclosed herein is a device using an oxide semiconductor, the device including a circuit part configured to include a thin film transistor using the oxide semiconductor as a channel material, wherein the circuit part has a lower interconnect, an upper interconnect, and an interlayer insulating film, the interlayer insulating film includes an oxide semiconductor layer and a channel protective layer, and the channel protective layer is interposed between an outer circumferential surface of a rising part of the oxide semiconductor layer corresponding to thickness of the lower interconnect and the upper interconnect.

Claims

1. A device using an oxide semiconductor, the device comprising:

a circuit part configured to include a thin film transistor using the oxide semiconductor as a channel material and at least one wiring intersection portion,

wherein the wiring intersection portion has an interlayer insulating film between a lower interconnect and an upper interconnect, the upper interconnect intersecting the lower interconnect,

wherein the interlayer insulating film includes an oxide semiconductor layer and a channel protective layer, the oxide semiconductor layer and the channel protective layer being stacked over the lower interconnect with intermediary of a gate insulating film, and

wherein the channel protective layer is interposed between an outer circumferential surface of a rising part of the oxide semiconductor layer corresponding to thickness of the lower interconnect and the upper interconnect.

2. The device using an oxide semiconductor according to claim 1, wherein a peripheral end of the oxide semiconductor layer is electrically short-circuited with the upper interconnect.

3. The device using an oxide semiconductor according to claim 2, wherein the peripheral end of the oxide semiconductor layer exists at the same outer circumferential position as an outer circumferential position of a peripheral end of the channel protective layer.

4. The device using an oxide semiconductor according to claim 1, wherein a peripheral end of the oxide semiconductor layer is electrically insulated from the upper interconnect.

5. A device using an oxide semiconductor, the device comprising:

a circuit part configured to include a thin film transistor using the oxide semiconductor as a channel material,

wherein the circuit part has an interlayer insulating film between a lower interconnect and an upper interconnect, the upper interconnect intersecting the lower interconnect, and

wherein the interlayer insulating film is over the lower interconnect with intermediary of a gate insulating film.

6. A device using an oxide semiconductor, the device comprising:

a circuit part configured to include a thin film transistor and at least one wiring intersection portion,

wherein the wiring intersection portion has an interlayer insulating film between a lower interconnect and an upper interconnect, the upper interconnect intersecting the lower interconnect, and

wherein the interlayer insulating film includes an oxide semiconductor layer and a protective layer, the oxide semiconductor layer and the protective layer being stacked over the lower interconnect with intermediary of a gate insulating film, and

wherein the protective layer is interposed between an outer circumferential surface of a rising part of the oxide semiconductor layer and the upper interconnect.

7. A display device comprising:

a pixel array part configured to be formed by arranging pixels each including an electrooptical element; and

a circuit part configured to include a thin film transistor using an oxide semiconductor as a channel material and at least one wiring portion,

wherein the wiring portion has an interlayer insulating film between a lower interconnect and a upper interconnect, the upper interconnect intersecting the lower interconnect, and

wherein the interlayer insulating film includes an oxide semiconductor layer and a channel protective layer, the oxide semiconductor layer and the channel protective layer being stacked over the lower interconnect with intermediary of a gate insulating film, and

wherein the channel protective layer is interposed between an outer circumferential surface of a rising part of the oxide semiconductor layer corresponding to thickness of the lower interconnect and the upper interconnect.

8. The display device according to claim 7, wherein the circuit part is mounted on the same substrate as a substrate of the pixel array part.

9. A display device comprising:

a pixel array part configured to be formed by arranging pixels each including an electrooptical element; and

a circuit part configured to include a thin film transistor using an oxide semiconductor as a channel material,

wherein the circuit part has an interlayer insulating film between a lower interconnect and an upper interconnect, the upper interconnect intersecting the lower interconnect, and

wherein the interlayer insulating film over the lower interconnect with intermediary of a gate insulating film.

10. The display device according to claim 9, wherein the circuit part is mounted on the same substrate as a substrate of the pixel array part.

11. Electronic apparatus having a display device comprising:

a pixel array part configured to be formed by arranging pixels each including an electrooptical element; and

a circuit part configured to include a thin film transistor using an oxide semiconductor as a channel material and at least one wiring intersection portion,

wherein the wiring intersection portion has an interlayer insulating film between a lower interconnect and an upper interconnect, the upper interconnect intersecting the lower interconnect, and

wherein the interlayer insulating film includes an oxide semiconductor layer and a channel protective layer, the oxide semiconductor layer and the channel protective layer being stacked over the lower interconnect with intermediary of a gate insulating film, and

wherein the channel protective layer is interposed between an outer circumferential surface of a rising part of the oxide semiconductor layer corresponding to thickness of the lower interconnect and the upper interconnect.

12. Electronic apparatus having a display device comprising:

a pixel array part configured to be formed by arranging pixels each including an electrooptical element; and

a circuit part configured to include a thin film transistor using an oxide semiconductor as a channel material,

wherein the circuit part has an interlayer insulating film between a lower interconnect and an upper interconnect, the upper interconnect intersecting the lower interconnect, and

wherein the interlayer insulating film is over the lower interconnect with intermediary of a gate insulating film.