Trench poly ESD formation for trench MOS and SGT

• US 8,476,676 B2
• Filed: 01/20/2011
• Issued: 07/02/2013
• Est. Priority Date: 01/20/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Chang, Hong, Chen, John
• Primary Examiner(s): TRAN, MINH LOAN
• Application Number:
  US13/010,427
• Publication Number:
  US 20120187472A1
• Time in Patent Office: 894 Days
• Field of Search: 257/173, 257/328, 257/330, 257/E29.262, 257/E21.41, 438/270
• US Class Current: 257/173
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device and its method of fabrication are described. A trench formed in a semiconductor substrate is partially filling said trench with a semiconductor material that lines a bottom and sides of the trench, leaving a gap in a middle of the trench running lengthwise along the trench. A first portion of the semiconductor material located below the gap is doped with dopants of a first conductivity type. The gap is filled with a dielectric material. Second portions of the semiconductor material located on the sides of the trench on both sides of the dielectric material are doped with dopants of a second conductivity type. The doping forms a P-N-P or N-P-N structure running lengthwise along the trench with differently doped regions located side by side across a width of the trench.

Claims

1. A method for fabricating a semiconductor device, comprising:

a) forming a trench in a semiconductor substrate;

b) partially filling said trench with a semiconductor material, such that the semiconductor material lines a bottom and sides of the trench, while leaving a gap in a middle of the trench running lengthwise along the trench;

c) doping a first portion of the semiconductor material located below the gap with dopants of a first conductivity type;

d) filling the gap with a dielectric material;

e) doping second portions of the semiconductor material located on the sides of the trench on both sides of the dielectric material with dopants of a second conductivity type, whereby the doping forms a P-N-P or N-P-N structure running lengthwise along the trench with differently doped regions located side by side across a width of the trench.

2. The method of claim 1, further comprising forming an additional semiconductor device in additional trenches formed in the semiconductor substrate.

3. The method of claim 2, wherein the additional semiconductor device is metal oxide semiconductor field effect transistor (MOSFET) or insulated gate bipolar transistor (IGBT).

4. The method of claim 2, wherein one or more elements of the additional semiconductor device are formed concurrently with corresponding elements of the semiconductor device.

5. The method of claim 4, wherein the one or more elements of the additional semiconductor device include one or more active gate trenches, wherein the one or more active gate trenches are formed concurrently with a).

6. The method of claim 2, wherein the N-P-N or P-N-P structure is part of an electrostatic discharge (ESD) protection structure for the additional semiconductor device, wherein the first and second portions of the semiconductor material are electrically connected to the additional semiconductor device.

7. The method of claim 6, wherein the additional semiconductor device includes a source and a gate, wherein one side of ESD protection structure is connected to source, the other side is connected to gate.

8. The method of claim 7, wherein the additional semiconductor device is a shielded gate transistor (SGT) device having a shield electrode formed in a common trench with the gate, wherein the gate is electrically isolated from the shield electrode by an inter-electrode dielectric, wherein forming the additional semiconductor device includes disposing a cover mask over the ESD protection structure during subsequent processing to finish the additional device.

9. The method of claim 1, further comprising lining the trench with a dielectric layer before partially filling the trench with the semiconductor material.

10. The method of claim 1, wherein forming the trench includes forming a hard mask on a surface of the semiconductor substrate, forming an opening in the hard mask corresponding to the trench and etching the substrate through the opening.

11. The method of claim 10, wherein forming the trench further includes forming etch-resistant insulating spacers along sidewalls of the opening in the hard mask to align the etching of the substrate, wherein the spacers are made of a material that is resistant to an process used to etch the substrate through the opening.

12. The method of claim 1, further comprising, after c) removing a selected amount of the first portion of the semiconductor material.

13. The method of claim 12, further comprising diffusing the dopants of the first conductivity type, wherein removing the selected amount of the first portion of the semiconductor material takes place after c) but before diffusing the dopants of the first conductivity type.

14. A semiconductor device, comprising:

a semiconductor material disposed in a trench, with poly lining at least the bottom of the trench, wherein the semiconductor material includes differently doped regions configured as a PNP or NPN structure formed in the trench with differently doped regions located side by side across a width of the trench, wherein the PNP or NPN structure includes first doped semiconductor regions along sidewalls of the trench and an oppositely-doped second semiconductor region located between the first semiconductor regions with a dielectric material filling a gap between the first semiconductor regions and above the second semiconductor region.

15. The device of claim 14, further comprising an additional semiconductor device formed in additional trenches in the semiconductor substrate.

16. The device of claim 15, wherein the additional semiconductor device is metal oxide semiconductor field effect transistor (MOSFET) or insulated gate bipolar transistor (IGBT).

17. The device of claim 15, wherein the N-P-N or P-N-P structure is part of an electrostatic discharge (ESD) protection structure for the additional semiconductor device, wherein the first and second portions of the semiconductor material are electrically connected to the additional semiconductor device.

18. The device of claim 17, wherein the additional semiconductor device includes a source and a gate, wherein one side of ESD protection structure is connected to source, the other side is connected to gate.

19. The device of claim 18, wherein the additional semiconductor device is a shielded gate transistor (SGT) device having a shield electrode formed in a common trench with the gate, wherein the gate is electrically isolated from the shield electrode by an inter-electrode dielectric.