Memory device and method for making same

• US 8,476,686 B2
• Filed: 07/09/2008
• Issued: 07/02/2013
• Est. Priority Date: 07/09/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Tilke, Armin
• Primary Examiner(s): Ingham, John C
• Application Number:
  US12/169,648
• Publication Number:
  US 20100008122A1
• Time in Patent Office: 1,819 Days
• Field of Search: 257/295, 257/E27.004, 365/163
• US Class Current: 257/295
• CPC Class Codes: H01L 29/66242 Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H10B 63/32 of the bipolar type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

An embodiment relates to a memory cell comprising a programmable resistance memory element electrically coupled to a heterojunction bipolar transistor.

Claims

1. A memory array, comprising:

a plurality of memory cells arranged along a first direction and a second direction, each of said cells comprising a programmable resistance memory element electrically coupled to a heterojunction bipolar transistor, said heterojunction bipolar transistor of each of said memory cells being an access device, said heterojunction bipolar transistor of each of said memory cells including a collector region, said collector regions being spaced apart from each other along said first direction and along said second direction.

2. The memory array of claim 1, wherein said heterojuction bipolar transistor is a SiGe heterojunction bipolar transistor including a SiGe base layer.

3. The memory array of claim 2, wherein said SiGe base includes the element carbon.

4. The memory array of claim 1, said transistor is a SiGe:

C heterojunction bipolar transistor including a SiGe;

C base layer.

5. The memory array of claim 1, wherein said memory element is electrically coupled in series with said transistor.

6. The memory array of claim 1, wherein each of said transistors includes an emitter region and a base region, said memory element being electrically coupled between a bitline and said emitter region, said base region electrically coupled to a wordline.

7. The memory array of claim 1, wherein said collector regions are spaced apart from each other along said first direction by first insulating trenches and wherein said collector regions are spaced apart from each other along said second direction by second insulating trenches.

8. The memory array of claim 7 wherein said first insulating trenches are oriented in said second direction and said second insulating trenches are oriented in said first direction.

9. The memory array of claim 7, wherein said insulating trenches directly contact a buried layer, said buried layer underlying said collector regions.

10. The memory array of claim 1, wherein said first direction is perpendicular to said second direction.

11. The memory array of claim 1, further comprising:

a plurality of wordlines; and

a plurality of bitlines,

wherein said first direction is parallel to said wordlines and said second direction is parallel to said bitlines.

12. The memory array of claim 1, wherein said memory array is configured in a NOR architecture.

25. The memory array of claim 1, wherein said programmable resistance memory element of each of said cells is a phase-change memory element.

13. A memory array, comprising:

a plurality of memory cells, each of said cells comprising a programmable resistance memory element electrically coupled to a heterojunction bipolar transistor, said heterojunction bipolar transistor of each of said memory cells being an access device, said heterojunction bipolar transistor of each of said memory cells including a collector region, each of said collector regions being spaced apart from all other collector regions of said memory array.

14. The memory array of claim 13, wherein said collector regions are spaced apart by insulating trenches.

15. The memory array of claim 14, wherein said insulating trenches directly contact a buried layer, said buried layer underlying said collector regions.

16. The memory array of claim 13, wherein said heterojuction bipolar transistor is a SiGe heterojunction bipolar transistor including a SiGe base layer.

17. The memory array of claim 16, wherein said SiGe base includes the element carbon.

18. The memory array of claim 13, said transistor is a SiGe:

C heterojunction bipolar transistor including a SiGe;

C base layer.

19. The memory array of claim 13, wherein said memory element is electrically coupled in series with said transistor.

20. The memory array of claim 13, wherein each of said transistors includes an emitter region and a base region, said memory element being electrically coupled between a bitline and said emitter region, said base region electrically coupled to a wordline.

21. The memory array of claim 13, wherein said memory array is configured in a NOR architecture.

22. The memory array of claim 13, wherein each of said collector regions being spaced apart from all other collector regions of said memory array by a dielectric.

23. The memory array of claim 22, wherein said dielectric directly contacts a buried layer, said buried layer underlying said collector regions.

24. The memory array of claim 23, wherein said buried layer electrically couples each of said collector regions to a common potential.

26. The memory array of claim 13, wherein said programmable resistance memory element of each of said cells is a phase-change memory element.