CMOS having a SiC/SiGe alloy stack

• US 8,476,706 B1
• Filed: 01/04/2012
• Issued: 07/02/2013
• Est. Priority Date: 01/04/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Greene, Brian J., Liang, Yue, Yu, Xiaojun
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US13/343,472
• Publication Number:
  US 20130168695A1
• Time in Patent Office: 545 Days
• Field of Search: 257/338, 257/351, 257/369, 257/371, 257/E27.064, 257/E27.067, 257/E27.108
• US Class Current: 257/338
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation

Abstract

A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.

Claims

1. A semiconductor structure comprising a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) located on a substrate,

wherein said PFET comprises a first silicon portion and a layer stack of a first silicon carbon alloy layer and a silicon germanium alloy layer, a combination of said first silicon portion and said layer stack includes a first source region, a first drain region, and a first body region, and said layer stack is in contact with a first gate dielectric that is in contact with a first gate electrode,

and wherein said NFET comprises a second silicon portion and a second silicon carbon alloy layer, a combination of said second silicon portion and said second silicon carbon alloy layer includes a second source region, a second drain region, and a second body region, and said second silicon carbon alloy layer is in contact with a second gate dielectric that is in contact with a second gate electrode,

and wherein said first gate dielectric and said second gate dielectric have a same composition and a same thickness.

2. The semiconductor structure of claim 1, wherein said first silicon carbon alloy layer and said second silicon carbon alloy layer have a same thickness and a same carbon concentration profile.

3. The semiconductor structure of claim 2, wherein said same thickness is not greater than 2.0 nm.

4. The semiconductor structure of claim 2, wherein said same carbon concentration profile has an atomic carbon concentration between 0.1% and 50% at a peak concentration.

5. The semiconductor structure of claim 2, wherein said first silicon carbon alloy layer and said second silicon carbon alloy layer comprise a single crystalline silicon carbon alloy material that is epitaxially aligned to an underlying silicon-containing single crystalline semiconductor material.

6. The semiconductor structure of claim 1, wherein said first silicon carbon alloy layer is in contact with a surface of said first gate dielectric.

7. The semiconductor structure of claim 1, wherein said silicon germanium alloy layer is in contact with a surface of said first gate dielectric.

8. The semiconductor structure of claim 1, wherein said first gate electrode and said second gate electrode have a same material composition and a same thickness.

9. The semiconductor structure of claim 1, further comprising a silicon oxide material portion located within said substrate and in contact with at least one of said first source region and said first drain region, and in contact with at least one of said second source region and said second drain region, wherein said silicon oxide material portion is substantially free of carbon.

10. The semiconductor structure of claim 1, wherein said first silicon carbon alloy layer and said second silicon carbon alloy layer are horizontal layers located on a bulk semiconductor substrate.

11. The semiconductor structure of claim 1, wherein said first silicon carbon alloy layer and said second silicon carbon alloy layer are horizontal layers located on a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate.

12. The semiconductor structure of claim 1, wherein said first silicon carbon alloy layer and said second silicon carbon alloy layer are vertical layers and are located on sidewalls of semiconductor fin portions that are located on said substrate.