CMOS having a SiC/SiGe alloy stack
First Claim
1. A semiconductor structure comprising a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) located on a substrate,wherein said PFET comprises a first silicon portion and a layer stack of a first silicon carbon alloy layer and a silicon germanium alloy layer, a combination of said first silicon portion and said layer stack includes a first source region, a first drain region, and a first body region, and said layer stack is in contact with a first gate dielectric that is in contact with a first gate electrode,and wherein said NFET comprises a second silicon portion and a second silicon carbon alloy layer, a combination of said second silicon portion and said second silicon carbon alloy layer includes a second source region, a second drain region, and a second body region, and said second silicon carbon alloy layer is in contact with a second gate dielectric that is in contact with a second gate electrode,and wherein said first gate dielectric and said second gate dielectric have a same composition and a same thickness.
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Accused Products
Abstract
A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.
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Citations
12 Claims
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1. A semiconductor structure comprising a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) located on a substrate,
wherein said PFET comprises a first silicon portion and a layer stack of a first silicon carbon alloy layer and a silicon germanium alloy layer, a combination of said first silicon portion and said layer stack includes a first source region, a first drain region, and a first body region, and said layer stack is in contact with a first gate dielectric that is in contact with a first gate electrode, and wherein said NFET comprises a second silicon portion and a second silicon carbon alloy layer, a combination of said second silicon portion and said second silicon carbon alloy layer includes a second source region, a second drain region, and a second body region, and said second silicon carbon alloy layer is in contact with a second gate dielectric that is in contact with a second gate electrode, and wherein said first gate dielectric and said second gate dielectric have a same composition and a same thickness.
Specification