Off-chip VIAS in stacked chips

• US 8,476,774 B2
• Filed: 12/12/2011
• Issued: 07/02/2013
• Est. Priority Date: 10/10/2006
• Status: Expired due to Fees

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Mohammed, Ilyas, Oganesian, Vage, Ovrutsky, David, Mirkarimi, Laura Wills
• Primary Examiner(s): Wagner, Jenny L
• Application Number:
  US13/316,890
• Publication Number:
  US 20120080807A1
• Time in Patent Office: 568 Days
• Field of Search: 257/786, 257/777, 257/E23.178
• US Class Current: 257/786
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/5382 : Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

Claims

1. An in-process microelectronic assembly comprising:

a first substrate;

a first microelectronic element comprising a front face bonded to said first substrate and an opposing rear face;

said first microelectronic element further comprising a plurality of first traces extending along said front face, at least a portion of each said first trace extending beyond a first edge of said first microelectronic element, said first microelectronic element further comprising a second edge opposite said first edge;

a second microelectronic element comprising a front face facing said opposing rear face of said first microelectronic element, said second microelectronic element further comprising a plurality of second traces extending along said front face of said second microelectronic element, at least a portion of each said second trace extending beyond a first edge of said second microelectronic element, said second microelectronic element further comprising a second edge opposite said first edge of said second microelectronic element;

a third microelectronic element comprising a front face bonded to said first substrate and an opposing rear face;

said third microelectronic element further comprising a plurality of third traces extending along said front face, at least a portion of each said third trace extending beyond a first edge of said third microelectronic element, said third microelectronic element further comprising a second edge opposite said first edge of said third microelectronic element, said third microelectronic element being adjacent to said first microelectronic element;

a fourth microelectronic element comprising a front face facing said opposing rear face of said third microelectronic element, said fourth microelectronic element further comprising a plurality of fourth traces extending along said front face of said fourth microelectronic element, at least a portion of each said fourth trace extending beyond a first edge of said fourth microelectronic element, said fourth microelectronic element further comprising a second edge opposite said first edge of said fourth microelectronic element;

a first insulating region disposed around respective said first and second edges of said first and third microelectronic elements;

a second insulating region disposed around respective said first and second edges of said second and fourth microelectronic elements, said first and second insulating regions defining at least (i) first and second side external surfaces adjacent the first and second edges of each of the first and second microelectronic elements and (ii) third and fourth side external surfaces adjacent the third and fourth edges of each of the third and fourth microelectronic elements; and

at least one electrical conductor disposed on at least one of said first, second, third, and fourth side external surfaces of said microelectronic assembly, said electrical conductor being in electrical contact with a cross-sectional edge of at least one of said plurality of said first, second, third, and fourth traces.

2. The microelectronic assembly of claim 1, wherein at least said first and second edges of said second microelectronic element are substantially aligned with said first and second edges of said first microelectronic element.

3. The microelectronic assembly of claim 1, wherein at least said first edge of said second microelectronic element is laterally offset from said first edge of said first microelectronic element.

4. The microelectronic assembly of claim 1, wherein at least each of said first and second microelectronic elements comprises a flash memory.

5. The microelectronic assembly of claim 1, wherein said at least one electrical conductor is disposed on at least one of said first and second side external surfaces and on at least one of said third and fourth side external surfaces of said microelectronic assembly.