System level interconnect with programmable switching

• US 8,476,928 B1
• Filed: 08/03/2011
• Issued: 07/02/2013
• Est. Priority Date: 04/17/2007
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sullam, Bert, Snyder, Warren, Mohammed, Haneef
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US13/197,624
• Time in Patent Office: 699 Days
• Field of Search: 326 39- 41, 326/47
• US Class Current: 326/41
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories

Abstract

Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers.

Claims

1. An apparatus, comprising:

different functional elements all located in a same integrated circuit wherein at least one of the functional elements comprises a micro-controller;

configuration registers or configuration memory in the integrated circuit to store configuration values;

different I/O pins configured to connect the integrated circuit to external signals; and

a system level interconnect, located in the integrated circuit, configured to programmably connect a first functional element to a first I/O pin and to connect the first functional element to the micro-controller according to the configuration values loaded into the configuration registers or configuration memory.

2. The apparatus of claim 1, wherein the system level interconnect is configured to dynamically change the connections between the different functional elements and the different I/O pins in real time according to different operational states of the integrated circuit.

3. The apparatus of claim 1, wherein the micro-controller is configured to load the configuration values into the configuration registers or configuration memory.

4. The apparatus of claim 1, wherein:

the functional elements further include multiple digital blocks that each include an arithmetic sequencer formed from programmable logic device sections comprising uncommitted user programmable logic functions and datapath sections comprising structural arithmetic elements;

the system level interconnect is programmably configurable to connect different selectable programmable logic device sections in the digital blocks to other different selectable functional elements and to different selectable I/O pins; and

the system level interconnect is programmably configurable to connect different selectable datapath sections in the digital blocks to other different selectable functional elements and to different selectable I/O pins.

5. The apparatus of claim 1, wherein:

the system level interconnect is configured to operate the first I/O pins as an input pin by coupling the first I/O pin to an input for one of the functional elements while the integrated circuit is in a first operational state; and

the system level interconnect is further configured to operate the first I/O pin as an output pin by coupling the first I/O pin to an output for one of the functional elements while the integrated circuit is in a second operational state.

6. The apparatus of claim 1, wherein the system level interconnect is configured to synchronously multiplex analog signals from different I/O pins to a same functional element that operates as an analog to digital converter.

7. The apparatus of claim 1, wherein the system level interconnect comprises horizontal channels configured to:

programmably couple to the different functional elements according to the configuration values in the configuration registers or configuration memory; and

programmably couple to the different I/O pins according to the configuration values in the configuration registers or configuration memory.

8. The apparatus of claim 7, further comprising;

a channel switch to programmably couple a first horizontal channel to the first functional element according to the configuration values; and

a segmentation switch to programmably couple the first horizontal channel to a second horizontal according to the configuration values.

9. The apparatus of claim 1, further comprising:

a first set of interface lines coupled to different associated functional elements; and

a second set of interface lines coupled to different associated I/O pins, the first and second sets of interface lines overlapping with multiple different channel lines in associated channels of the system level interconnect and programmably coupled to the different channel lines according to the configuration values.

10. The apparatus of claim 9, further comprising:

hold cells configured to retain a last state on associated interface lines and further configured to set the associated interface lines to a weak predetermined state upon receiving a reset signal.

11. An integrated circuit, comprising:

an interconnect configured to programmably couple different selectable functional elements to different selectable I/O pins in the integrated circuit according to configuration values, the interconnect configured to be programmably changed in real-time while the integrated circuit is in operation,

wherein the interconnect comprises different sets of interface lines and different sets of channel lines, the interface lines selectively coupled to the different selectable functional elements, the different selectable I/O pins, and the different channel lines according to the configuration values.

12. The integrated circuit of claim 11, wherein the different channel lines programmably couple the different functional elements in the integrated circuit and the different I/O pins in the integrated circuit according to the configuration values.

13. The integrated circuit of claim 12, further comprising:

segmentation elements to programmably couple the channels together according to the configuration values.

14. The integrated circuit of claim 12, further comprising:

an array of universal digital blocks comprising uncommitted programmable logic sections and structural arithmetic logic sections, the interconnect programmably configured to connect different programmable logic sections and different arithmetic logic sections to the different channel lines in the interconnect.

15. An apparatus, comprising:

different functional elements comprising a micro-controller, a first peripheral, and a second peripheral, all located in a same integrated circuit;

configuration registers or configuration memory in the integrated circuit to store configuration values;

different I/O pins configured to connect the integrated circuit to external signals; and

a system level interconnect located in the integrated circuit to programmably connect the different functional elements to different I/O pins according to the configuration values loaded into the configuration registers or configuration memory,

wherein the system level interconnect is configured to be programmed according to the configuration values to couple a first I/O pin to the first peripheral while the integrated circuit is in a first state and couple the first I/O pin to the second peripheral when the integrated circuit is in a second state.

16. The apparatus of claim 15, further comprising:

a first set of interface lines coupled to different associated functional elements; and

a second set of interface lines coupled to different associated I/O pins, the first and second sets of interface lines overlapping with multiple different channel lines in associated channels of the system level interconnect and programmably coupled to the different channel lines according to the configuration values.

17. The apparatus of claim 16, wherein multiple interface lines associated with the same functional elements or associated with the same I/O pins are shorted together.

18. The apparatus of claim 17, wherein each of the multiple shorted interface lines are configured to be programmably coupled to different channel lines according to the configuration values.

19. The apparatus of claim 15, wherein the first peripheral comprises an analog peripheral.

20. The apparatus of claim 15, wherein the second peripheral comprises a digital peripheral.