3D integrated circuit stack-wide synchronization circuit

• US 8,476,953 B2
• Filed: 08/25/2011
• Issued: 07/02/2013
• Est. Priority Date: 08/25/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Silberman, Joel A., Wordeman, Matthew R.
• Primary Examiner(s): POOS, JOHN W
• Application Number:
  US13/217,767
• Publication Number:
  US 20130049825A1
• Time in Patent Office: 677 Days
• Field of Search: 327/291, 327/293, 327/295, 327/403, 327/415
• US Class Current: 327/291
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

Claims

1. A stack-wide synchronization circuit for providing a stack-wide synchronous signal to each stratum of a 3D chip stack having multiple circuits and two or more strata interconnected using at least a first and a second connection chain, each of the first and the second connection chains being in a stack-wide broadcast configuration, the stack-wide synchronization circuit comprising, on each of the two or more strata:

a synchronizer, connected to the first connection chain, for receiving an asynchronous signal therefrom and performing a synchronization of the asynchronous signal to a clock signal to provide a synchronous signal with respect to the clock signal;

a driver, connected to the second connection chain, for driving the synchronous signal; and

a latch, connected to the second connection chain, for receiving the synchronous signal driven by the driver on a same one or a different one of the two or more strata within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to at least one of the multiple circuits on a same one of the two or more strata,

wherein the driver on each of the two or more strata is configured such that an output of a single driver on one of the two or more strata is selected at any given time for use by the latch on all of the two or more strata.

2. The stack-wide synchronization circuit of claim 1, wherein the driver is a tri-state driver.

3. The stack-wide synchronization circuit of claim 1, wherein the driver is a multiplexer.

4. The stack-wide synchronization circuit of claim 1, wherein the driver on each of the two or more strata is responsive to one or more programming bits that specify the single selected driver.

5. The stack-wide synchronization circuit of claim 4, wherein the synchronous signal provided by only the single selected driver is used by the latch on each of the two or more strata to provide the stack-wide synchronous signal therefrom.

6. The stack-wide synchronization circuit of claim 1, further comprising asynchronous inputs, connected to the first connection chain on each of the two or more strata, for initially receiving the asynchronous signal into the 3D chip stack.

7. The stack-wide synchronization circuit of claim 1, wherein at least some of the asynchronous inputs are accessible externally with respect to the 3D chip stack.

8. The stack-wide synchronization circuit of claim 1, wherein the asynchronous inputs comprise at least one of input pads and C4 connections.

9. The stack-wide synchronization circuit of claim 1, wherein the clock signal is provided to each of the two or more strata.

10. The stack-wide synchronization circuit of claim 1, wherein the synchronizer, the driver, and the latch on the same one of the two or more strata are serially connected in a chain having as taps the first connection chain and the second connection chain.

11. The stack-wide synchronization circuit of claim 1, wherein the first connection chain comprises a plurality of through-and-through vias, each of the plurality of through-and-through vias having a front-side connection and a backside connection co-located and connected to the front-side connection, the front-side connection being connected to the first connection point on same one of the two or more strata.

12. A method for providing a stack-wide synchronous signal to each stratum of a 3D chip stack having multiple circuits and two or more strata interconnected using at least a first and a second connection chain, each of the first and the second connection chains being in a stack-wide broadcast configuration, the method comprising:

providing on each of the two or more strata;

a synchronizer, connected to the first connection chain, configured to receive an asynchronous signal therefrom and perform a synchronization of the asynchronous signal to a clock signal to provide a synchronous signal with respect to the clock signal;

a driver, connected to the second connection chain, configured to drive the synchronous signal; and

a latch, connected to the second connection chain, configured to receive the synchronous signal driven by the driver on a same one of a different one of the two or more strata within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to at least one of the multiple circuits on a same one of the two or more strata,

wherein the method comprises configuring the driver on each of the two or more strata such that an output of a single driver on one of the two or more strata is selected at any given time for use by the latch on all of the two or more strata.

13. The method of claim 12, wherein the driver is a tri-state driver.

14. The method of claim 12, wherein the driver is a multiplexer.

15. The method of claim 12, further comprising configuring the driver on each of the two or more strata to be responsive to one or more programming bits that specify the single selected driver.

16. The method of claim 15, wherein the synchronous signal provided by only the single selected driver is used by the latch on each of the two or more strata to provide the stack-wide synchronous signal therefrom.

17. The method of claim 12, further comprising providing asynchronous inputs, connected to the first connection chain, configured to initially receive the asynchronous signal into the 3D chip stack.

18. The method of claim 12, further comprising configuring at least some of the asynchronous inputs to be externally accessible with respect to the 3D chip stack.

19. The method of claim 12, wherein the asynchronous inputs comprise at least one of input pads and C4 connections.

20. The method of claim 12, further comprising providing the clock signal to each of the two or more strata.

21. The method of claim 12, wherein the synchronizer, the driver, and the latch on the same one of the two or more strata are serially connected in a chain having as taps the first connection chain and the second connection chain.

22. A method for providing a stack-wide synchronous signal to each stratum of a 3D chip stack having multiple circuits and two or more strata interconnected using at least a first and a second connection chain, each of the first and the second connection chains being in a stack-wide broadcast configuration, the method comprising:

with respect to each of the two or more strata;

receiving an asynchronous signal;

performing a synchronization of the asynchronous signal to a clock signal to provide a synchronous signal with respect to the clock signal;

receiving the synchronous signal driven by a driver on a same one or a different one of the two or more strata; and

latching the synchronous signal within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to at least one of the multiple circuits on a same one of the two or more strata,

wherein a driver is provided on each of the two or more strata and is configured such that an output of a single driver on one of the two or more strata is selected at any given time to provide the synchronous signal on each of the two or more strata for said step of receiving the synchronous signal.

23. The method of claim 22, wherein the driver on each of the two or more strata is responsive to one or more programming bits that specify the single selected driver.

24. A stack-wide synchronization circuit for synchronizing an asynchronous signal in each stratum of a 3D chip stack having two or more strata interconnected using at least a first and a second chain of vias, each of the first and the second chain of vias being in a stack-wide broadcast configuration, the stack-wide synchronization circuit comprising, on each of the two or more strata:

a first connection point for receiving the asynchronous signal;

an off-chip receiver having an input and an output, the input connected to the connection point;

an asynchronous-to-synchronous signal converter having an input connected to an output of the off-chip receiver;

a tri-state driver having a non-selection input connected an output of the asynchronous-to-synchronous signal converter;

a second connection point, connected to an output of the tri-state driver;

an inter-strata receiver having an input connected to the second connection point; and

a staging latch having an input connected to an output of the inter-strata receiver,

wherein the first connection point is connected to the first chain of vias and the second connection point is connected to the second chain of vias, the tri-state drivers are configured such that an output of a single tri-state driver on one of the two or more strata is selected at any given time, and wherein the output of the staging latch on each of the two or more strata provides a stack-wide synchronous signal during a given clock cycle responsive to a receipt of the asynchronous input signal by the first connection point on any of the two or more strata during an immediately preceding clock cycle with respect to the given clock cycle.

25. The stack-wide synchronization circuit of claim 24, wherein the driver on each of the two or more strata is responsive to one or more programming bits that specify the single selected driver.