Stable driving scheme for active matrix displays

• US 8,477,121 B2
• Filed: 04/18/2007
• Issued: 07/02/2013
• Est. Priority Date: 04/19/2006
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Nathan, Arokia, Chaji, G. Reza
• Primary Examiner(s): Pervan, Michael
• Application Number:
  US11/736,751
• Publication Number:
  US 20070247398A1
• Time in Patent Office: 2,267 Days
• Field of Search: 345 76- 83, 345/204, 345/84, 345 87-104, 345208-210
• US Class Current: 345/204
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0866 by means of changes in the pixel supply voltage
• CPC Class Codes: G09G 2310/0254 Control of polarity reversal in general, other than for liquid crystal displays
• CPC Class Codes: G09G 2310/0256 with the purpose of reversing the voltage across a light emitting or modulating element within a pixel
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element

Abstract

A method and system for operating a pixel array having at least one pixel circuit is provided. The method includes repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit, driving the pixel circuit, and relaxing a stress effect on the pixel circuit, prior to a next frame period. The system includes a pixel array including a plurality of pixel circuits and a plurality of lines for operation of the plurality of pixel circuits. Each of the pixel circuits includes a light emitting device, a storage capacitor, and a drive circuit connected to the light emitting device and the storage capacitor. The system includes a drive for operating the plurality of lines to repeat an operation cycle having a frame period so that each of the operation cycle comprises a programming cycle, a driving cycle and a relaxing cycle for relaxing a stress on a pixel circuit, prior to a next frame period.

Claims

1. A method of operating a pixel array having at least one pixel circuit, the pixel circuit including a switch, a select line connected to the switch, a drive transistor coupled to a data line via the switch and to a power supply line, a light emitting device coupled to the drive transistor, and a storage capacitor coupled to the drive transistor, the method comprising:

repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period;

programming during the operation cycle the pixel circuit responsive to driving the select line from a first state to a second state to select the pixel for programming, the programming including providing a programming data on the data line;

responsive to the programming, driving the pixel circuit during a driving cycle of the operation cycle responsive to driving the select line from the second state to the first state; and

responsive to the driving, relaxing a stress effect on the pixel circuit during a relaxing cycle of the operation cycle, prior to a next frame period, the relaxing including driving the select line from the first state to the second state during a first operating cycle of the relaxing cycle followed by driving the select line from the second state to the first state during a second operating cycle of the relaxing cycle so that the pixel circuit is off during said the second operating cycle, the relaxing further including, during the first operating cycle, changing the data line to a voltage smaller than V_T0+V_OLED0, where V_TO is a threshold voltage of the drive transistor in an unstressed state and V_OLED0 is an ON voltage of the light emitting device in an unstressed state, wherein the pixel circuit is off at the second operating cycle, and wherein the power supply line has a positive voltage during the driving driving cycle and the relaxing cycle.

2. A method as claimed in claim 1, wherein the relaxing comprises:

turning the pixel circuit off.

3. A method as claimed in claim 1, wherein the relaxing comprises:

biasing the pixel circuit with a reverse polarity relative to a polarity of the pixel circuit during the driving.

4. A method as claimed in claim 1, wherein the programming comprises:

at a first cycle, developing a voltage across the gate-source voltage of the drive transistor.

5. A method as claimed in claim 4, wherein the developing comprises:

charging the power supply line to a first voltage and charging the data line to a second voltage with a reverse polarity of the first voltage.

6. A method as claimed in claim 5 wherein the drive transistor has a gate terminal and first and second terminals, the gate terminal being connected to the data line via the switch, and wherein the first terminal of the drive transistor is connected to the power supply line and the second terminal of the drive transistor is connected to the light emitting device, a first terminal of the storage capacitor being connected to the gate terminal of the drive transistor, a second terminal of the storage capacitor being connected to the second terminal of the drive transistor and the light emitting device.

7. A method as claimed in claim 4, wherein the programming comprises:

at a second cycle subsequent to the first cycle, operating on the pixel circuit so that a voltage of a connection point between the light emitting device and the drive transistor and the storage capacitor is the second voltage of the data line minus a threshold voltage of the drive transistor.

8. A method as claimed in claim 7 wherein the programming comprises:

at a third cycle subsequent to the second cycle, charging the data line to a programming voltage associated with a programming data.

9. A method as claimed in claim 4, wherein the programming comprises:

at a second cycle subsequent to the first cycle, operating on the pixel circuit so that a voltage stored in the storage capacitor is a threshold voltage of the drive transistor.

10. A method as claimed in claim 9 wherein the programming comprises:

at a third cycle subsequent to the second cycle, programming the pixel circuit by a voltage defined by;

11. A method as claimed in claim 4 wherein the programming comprises:

at a second cycle subsequent to the first cycle, charging the power supply line to a third voltage, the third voltage being identical to a voltage for driving the pixel circuit.

12. A method as claimed in claim 4 wherein the programming comprises:

at a second cycle subsequent to the first cycle, charging one of the first and second terminals of the drive transistor to a point at which the drive transistor turns off.

13. The method as claimed in claim 1, wherein the programming includes:

at a first cycle of the programming cycle, charging the power supply line to a first voltage having a reverse polarity of the voltage on the data line;

at a second cycle of the programming cycle subsequent to the first cycle, changing the voltage of the power supply line to a point at which the drive transistor turns off; and

at a third cycle of the programming cycle subsequent to the second cycle, providing the programming data on the data line by charging the data line to a programming voltage corresponding to the programming data.

14. The method as claimed in claim 1, wherein the relaxing includes:

during the second operating cycle of the relaxing, simultaneously programming a second pixel located in a row in the pixel array different from the row in which the first pixel is located by providing a second programming data for the second pixel on the data line responsive to driving a second select line from the first state to the second state.

15. A display system comprising:

a pixel array including a plurality of pixel circuits and a plurality of lines for operation of the plurality of pixel circuits, each of the pixel circuits having a switch, a select line connected to the switch, a light emitting device, a storage capacitor, and a drive transistor connected to the light emitting device and the storage capacitor, the drive transistor being connected to a data line via the switch and to a power supply line;

a driver for operating the plurality of lines to repeat an operation cycle having a frame period so that each of the operation cycle comprises a programming cycle, a driving cycle and a relaxing cycle for relaxing a stress on a pixel circuit of the pixel array, prior to a next frame period; and

a controller coupled to the driver, the controller operable to;

program during the programming cycle a first of the pixel circuits responsive to driving the select line from a first state to a second state to select the first pixel circuit for programming by providing a programming data on the data line,

responsive to programming the first pixel circuit, drive the first pixel circuit during the driving cycle responsive to driving the select line from the second state to the first state, and

responsive to driving the first pixel circuit, relax a stress effect on the first pixel circuit during the relaxing cycle, prior to the next frame period, by driving the select line from the first state to the second state during a first operating cycle of the relaxing cycle followed by driving the select line from the second state to the first state during a second operating cycle of the relaxing cycle so that the pixel circuit is off during the second operating cycle, wherein during the first operating cycle, the data line is changed to a voltage smaller than V_T0+V_OLED0, where V_TO is a threshold voltage of the drive transistor in an unstressed state and V_OLED0 is an ON voltage of the light emitting device in an unstressed state, wherein the first pixel circuit is off at the second operating cycle, and wherein the power supply line has a positive voltage during the driving cycle and the relaxing cycle.

16. A display system as claimed in claim 15, wherein the light emitting device is an organic light emitting diode.

17. A display system as claimed in claim 15, wherein the plurality of transistors are fabricated using fabricated using amorphous silicon, nano/micro crystalline silicon, poly silicon, organic semiconductors technology, NMOS/PMOS technology, CMOS technology, or combinations thereof.

18. A display system as claimed in claim 15 further comprising a controller for controlling the driver so that the programming cycle for a first row of the first pixel circuit occurs simultaneously during the second operating cycle of the relaxing cycle for a second pixel circuit in a second row.

19. The display system as claimed in claim 15, wherein the controller is further operable to:

at a first cycle of the programming cycle, charging the power supply line to a first voltage having a reverse polarity of the voltage on the data line;

at a second cycle of the programming cycle subsequent to the first cycle, changing the voltage of the power supply line to a point at which the drive transistor turns off; and

at a third cycle of the programming cycle subsequent to the second cycle, providing the programming data on the data line by charging the data line to a programming voltage corresponding to the programming data.