Methods and apparatuses for reducing step loads of processors

• US 8,479,029 B2
• Filed: 06/24/2011
• Issued: 07/02/2013
• Est. Priority Date: 09/11/2007
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Stackhouse, Blaine, Undy, Steve, Safford, Kevin, Bhatia, Rohit, Bostak, Chris, Blumberg, Richard
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Brown, Michael J.
• Application Number:
  US13/167,970
• Publication Number:
  US 20110252255A1
• Time in Patent Office: 739 Days
• Field of Search: 713/300, 713/320, 713/323, 713/340, 714/42
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken

Abstract

Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

Claims

1. An apparatus comprising:

determination logic to determine at least one type of instruction within an instruction stream to be executed by a core;

power calculation logic to calculate power consumption associated with processing of the instruction stream based on the at least one type of instruction;

throttling logic to limit a rate at which the instruction stream is to be processed based on the calculated power consumption;

an activity generator to generate artificial activity for a core to maintain a minimum power floor;

a core controller to control the activity generator and the throttling logic based upon the calculated power consumption; and

a system controller to enable a plurality of cores to operate at different power levels, wherein the system controller is to determine a minimum amount of time lapse before allowing one of the plurality of cores to change from a first power level to a second power level.

2. The apparatus of claim 1, further comprising a plurality of core controllers, wherein at least one of the plurality of core controllers is to request the system controller to change operation of a corresponding core from a first power level to a second power level.

3. The apparatus of claim 1, wherein the system controller is to grant a plurality of requests for the plurality of cores using a token-based scheme.

4. The apparatus of claim 1, wherein the throttling logic is to limit rates at which the instruction stream is to be processed by the core.

5. A system, comprising:

a plurality of cores;

a plurality of core controllers each associated with one of the plurality of cores and to control a power level of the corresponding core; and

a socket controller to monitor requests of the plurality of core controllers for changes to power levels of the plurality of cores, wherein the socket controller is to maintain an average power consumption, wherein the socket controller is to determine a minimum amount of time required before allowing one of the plurality of core controllers to cause a corresponding core to change from a first power level to a second power level.

6. The system of claim 5, wherein a first core controller is to request permission from the socket controller to change operation of a corresponding core from a first power level to a second power level.

7. The system of claim 5, further comprising a counter coupled to the socket controller to determine the minimum amount of time.

8. The system of claim 5, further comprising an activity generator associated with a first core to generate artificial activity for the core to maintain a minimum power floor.

9. A method comprising:

examining a plurality of instructions to be processed by a processor to determine types of instructions in the plurality of instructions;

calculating a quantity of power to be consumed by the processor in a period of execution based on the types of instructions;

limiting execution of the processor in the execution period to a first subset of instructions of a first power level, and thereafter allowing a second subset of instructions of a second power level to be executed; and

adjusting a created amount of artificial activity to maintain a minimum power floor, and creating the amount of artificial activity by one of turning on a clock to keep clock switching power constant, changing data patterns, and using power resistors.

10. The method of claim 9, further comprising adjusting the artificial activity, based upon the calculation of the quantity of power, to maintain operation of the at least one core of the processor within one power level of a plurality of power levels.

11. The method of claim 10, further comprising limiting execution of instructions of individual cores to control quantities of power of the individual cores and operating the individual cores within power levels having a respective maximum power level and a respective minimum power floor.

12. The method of claim 11, further comprising enabling the individual cores to operate at different power levels of the power levels to control overall power of the processor.

13. The method of claim 9, wherein the examining the plurality of instructions to determine the types of instructions comprises determining whether at least one of a memory instruction, a floating point instruction, a multimedia execution unit (MMU) instruction, and a single instruction multiple data (SIMD) instruction is present.

14. The method of claim 9, wherein the calculating the quantity of power to be consumed by the processor in the execution period includes calculating the quantity of power to be consumed by the processor in a clock cycle.

15. The method of claim 9, wherein the calculating the quantity of power to be consumed by the processor in the execution period includes calculating the quantity of power to be consumed by the processor in a plurality of clock cycles.