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Methods and apparatuses for reducing step loads of processors

  • US 8,479,029 B2
  • Filed: 06/24/2011
  • Issued: 07/02/2013
  • Est. Priority Date: 09/11/2007
  • Status: Expired due to Fees
First Claim
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1. An apparatus comprising:

  • determination logic to determine at least one type of instruction within an instruction stream to be executed by a core;

    power calculation logic to calculate power consumption associated with processing of the instruction stream based on the at least one type of instruction;

    throttling logic to limit a rate at which the instruction stream is to be processed based on the calculated power consumption;

    an activity generator to generate artificial activity for a core to maintain a minimum power floor;

    a core controller to control the activity generator and the throttling logic based upon the calculated power consumption; and

    a system controller to enable a plurality of cores to operate at different power levels, wherein the system controller is to determine a minimum amount of time lapse before allowing one of the plurality of cores to change from a first power level to a second power level.

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