Systems, methods and devices for regulation or isolation of backup power in memory devices

• US 8,479,032 B2
• Filed: 06/26/2009
• Issued: 07/02/2013
• Est. Priority Date: 06/26/2009
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Trantham, Jon David, Johnston, Darren Edward, Wilson, Dean Clark
• Primary Examiner(s): Vo, Tim T
• Assistant Examiner(s): VU, TRISHA U
• Application Number:
  US12/492,935
• Publication Number:
  US 20100332858A1
• Time in Patent Office: 1,467 Days
• Field of Search: 713300-340, 711/100, 711102-106
• US Class Current: 713/340
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a data-storage device is implemented having a memory control circuit controlling nonvolatile and volatile memory. An operating power circuit carries primary-operating power from the host-system to the memories and control circuitry. A backup power circuit includes energy-storage circuitry with one or more energy storage devices. An isolation-regulation circuit provides voltage regulation of power from the host-system and also isolates the host-system provided power from the energy storage devices. A regulation power circuit carries the regulated power from the isolation-regulation circuit to the energy storage devices.

Claims

1. A data-storage device comprising:

a memory control circuit;

a solid-state non volatile memory circuit for providing, under control of the memory control circuit, storage of data;

a volatile memory circuit having a primary-operating power and for storing, under control of the memory control circuit, write data destined for the solid-state nonvolatile memory circuit;

power circuitry for receiving electrical power from an external host-system power source and for providing the received electrical power for use as the primary-operating power; and

a backup power circuit including

an energy-storage circuit with one or more energy storage components designed to hold sufficient energy to provide substantially all of the primary-operating power during a minimum time period sufficient to permit data transfer, of at least dirty write data, from the volatile memory circuit to the nonvolatile memory circuit, and

an isolation-regulation circuit for providing voltage regulation of the electrical power received from the host-system power source, for providing the regulated voltage for charging of the energy storage circuit, and for isolating the host-system power source from the energy storage components in response to the power received from host-system power source dropping below a voltage threshold level.

2. The data storage device of claim 1 wherein the one or more energy storage components include one or more supercapacitors.

3. The data storage device of claim 2, further including a configuration circuit for determining a charging voltage level for charging the supercapacitor and wherein the isolation-regulation circuit is configured to provide the voltage regulation as a function of the determined charging voltage level.

4. The data storage device of claim 1, wherein the isolation-regulation circuit includes a buck-boost regulator that is configured to deliver a regulated voltage that is higher than a voltage of the power received from host-system power source.

5. The data storage device of claim 1, wherein the isolation-regulation circuit includes a buck regulator that can be configured to deliver a regulated voltage that is lower than a voltage of the power received from host-system power source.

6. The data storage device of claim 1, further including a power control circuit for generating a control signal as a function of detected power-providing capabilities of the energy storage circuit and wherein the isolation-regulation circuit includes a buck-boost regulator that controls a voltage level applied to the energy storage components in response to the control signal.

7. The data storage device of claim 1, wherein the isolation-regulation circuit is configured and arranged to control a charging voltage of the energy storage components substantially independent of a voltage of the power received from the host-system.

8. The data storage device of claim 1, wherein the isolation-regulation circuit includes a voltage regulator configured and arranged and to generate, from the received host-system power, a voltage, for charging a capacitor, that is substantially independent of a voltage of the primary-operating power.

9. The data storage device of claim 1, further including a housing structure for containing the circuits within a hard-disc form factor corresponding to one of:

5.75 inch×

1.63 inch×

8 inch;

4 inch×

1 inch×

5.75 inch;

0.59 inch×

2.8 inch×

3.9 inch, and 0.28 inch×

2.8 inch×

3.9 inch.

10. A data storage device comprising:

a hard-disc housing structure containing,

a power supply input for providing operating power;

a memory control circuit;

a nonvolatile, solid-state memory circuit for providing memory access, under control of the memory control circuit, to data;

a caching memory circuit having a primary-operating power input and for storing a cached version of the data, the caching memory circuit subject to loss of the cached version of the data in response to a voltage at a primary-operating power input dropping below a voltage threshold level;

an operating power circuit for carrying power the power supply input to the primary-operating power input of the caching memory circuit; and

a backup power circuit including

a power-reservoir circuit, including a capacitor, designed to hold a peak charge sufficient to provide substantially all power the primary-operating power input during a minimum time period sufficient to permit transfer of at least dirty data from the caching memory circuit to the nonvolatile memory circuit, and

a buck-boost regulator circuit for providing voltage regulation of power from the power supply input, for blocking power from flowing to the power supply input from the capacitor when the primary-operating power drops below the voltage threshold level and for dedicating use of the regulated power to the power-reservoir circuit.

11. The data storage device of claim 10, wherein the data storage device is designed to receive, on the power supply input, voltages within an operational voltage range that has a minimum voltage level and wherein the buck-boost regulator circuit is configured to regulate the power to a voltage higher than the minimum voltage level.

12. The data storage device of claim 10, wherein the data storage device is designed to receive, on the power supply input, voltages within an operational voltage range that has a maximum voltage level and wherein the buck-boost regulator circuit is configured to regulate the power to a voltage lower than the maximum voltage level.

13. The data storage device of claim 10, further including a test circuit for determining power providing capabilities of the capacitor and for generating a control signal in response to the determination and wherein the buck-boost regulator circuit is configured to adjust a voltage level of the regulated power in response to the control signal.

14. The data storage device of claim 10, wherein the hard-disc housing structure includes an interface for one of a Serial Advanced Technology Attachment (SATA), Advanced Technology Attachment (ATA), Fibre-Channel-Arbitrated-Loop (FCAL), IEEE-1394, Universal Serial Bus (USB), Serial Attached SCSI (SAS), and Parallel Small Computer System Interface (SCSI).

15. A method of using a data storage device, the method comprising:

providing access to data stored within a nonvolatile solid-state memory circuit under control of a memory control circuit;

caching data within a volatile memory circuit to facilitate the operation of the data storage device including access to the solid-state memory circuit;

delivering power received from a host-system power supply to the volatile memory circuit for use as primary-operating power;

storing, in one or more energy-storage components within an energy-storage circuit, an amount of energy sufficient to provide substantially all of the primary-operating power to the volatile memory circuit during a minimum time period sufficient to permit transfer of at least dirty data from the volatile memory circuit to the nonvolatile memory circuit;

regulating, using an isolation-regulation circuit, the power received from the host-system power supply;

isolating, using an isolation-regulation circuit, the power received from the host-system power source relative to the energy-storage circuitry in response to the host-system provided power dropping below a voltage threshold level; and

charging the energy-storage component using the regulated and isolated power from the isolation-regulation circuit.

16. The method of claim 15, wherein the step of regulating includes maintaining the regulated power within a voltage range.

17. The method of claim 15, wherein the step of regulating includes boosting a voltage level of the power from the host-system power supply.

18. The method of claim 15, further including the steps of testing the power providing capabilities of the energy-storage component, determining a value for the power providing capabilities as a function of the test and setting a voltage level for the regulated power to the energy-storage component as a function of the determined value.