Integrated circuit (IC) with primary and secondary networks and device containing such an IC

• US 8,479,069 B2
• Filed: 03/19/2010
• Issued: 07/02/2013
• Est. Priority Date: 09/19/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Miller, Marc, Teig, Steven, Hutchings, Brad, Thom, Danny
• Primary Examiner(s): Rizk, Sam
• Application Number:
  US12/728,194
• Publication Number:
  US 20110060546A1
• Time in Patent Office: 1,201 Days
• Field of Search: 714/734, 370/254
• US Class Current: 714/734
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G11C 2029/0409 Online test

Abstract

Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.

Claims

1. An integrated circuit (“

IC”

) comprising;

a primary routing network for performing a plurality of operations that implement a user design, the primary routing network comprising a plurality of configurable circuits; and

a secondary monitoring network for receiving a set of data from the primary routing network and performing performance analysis on the set of data, wherein said set of data comprises data that is at least one of (i) input and (ii) output data of a particular set of circuits of the primary routing network, wherein said secondary monitoring network comprises a network that overlays the primary routing network and is communicatively coupled to a plurality of the circuits of the primary routing network, wherein said performance analysis comprises measuring throughput at the particular set of circuits of the primary routing network.

2. The IC of claim 1, wherein said particular set of circuits of the primary routing network comprises a set of input/output (“

I/O”

) circuits of the IC.

3. The IC of claim 1, wherein said performance analysis comprises comparing the measured throughput against a predetermined throughput value, wherein the secondary monitoring network further comprises a trigger circuit for firing a trigger when said throughput does not exceed the predetermined throughput value.

4. The IC of claim 3, wherein said secondary monitoring network further comprises a trace buffer for storing another set of data of the primary routing network upon said firing of said trigger.

5. The IC of claim 4, wherein said other set of data comprises data values that indicate why the measured throughput does not exceed the predetermined value.

6. The IC of claim 1, wherein said IC is on a single substrate.

7. The IC of claim 1, wherein said primary routing network comprises a plurality of user design state (“

UDS”

) elements for storing user data used by the primary routing network in implementing the user design, wherein said network that overlays the primary routing network is communicatively coupled to one or more of said UDS elements.

8. The IC of claim 7, wherein said user data stored by said one or more UDS elements is the set of data upon which performance analysis is performed by the secondary monitoring network.

9. An integrated circuit (“

IC”

) comprising;

a primary routing network for performing a plurality of operations that implement a user design, the primary routing network comprising a plurality of circuits; and

a secondary monitoring network for receiving a set of data from the primary routing network and, as data packets are passing through the primary routing network, performing behavioral analysis on the set of data, wherein said behavioral analysis comprises counting the passing of a specified number of the data packets wherein said set of data comprises data that is at least one of (i) input and (ii) output data of a set of circuits of the primary routing network, wherein said secondary monitoring network comprises a network that overlays the primary routing network and is communicatively coupled to the plurality of circuits of the primary routing network.

10. The IC of claim 9, wherein said behavioral analysis further comprises determining whether at least one data value of said set of data meets a predetermined behavioral parameter.

11. The IC of claim 10, wherein said secondary monitoring network further comprises assertion circuitry for generating an assertion in response to said at least one data value meeting said predetermined behavioral parameter, wherein said assertion indicates that a modification should be made to at least one of (i) the primary routing network and (ii) the secondary monitoring network.

12. The IC of claim 10, wherein said behavioral parameter is for indicating a TCP-SYN attack.

13. The IC of claim 9, wherein said secondary monitoring network further comprises a memory for storing at least one data value of said set of data values, wherein the stored data value is supplied to a location external to the IC.

14. The IC of claim 13, wherein said at least one data value is stored in said memory upon determining, through said behavioral analysis, that said at least one data value meets a predetermined behavioral parameter.

15. The IC of claim 9, wherein said IC is on a single substrate.

16. The IC of claim 9, wherein said primary routing network comprises a plurality of user design state (“

UDS”

) elements for storing user data used by the primary routing network in implementing the user design, wherein said network that overlays the primary network is communicatively coupled to one or more of said UDS elements.

17. The IC of claim 16, wherein said user data stored by said one or more UDS elements is the set of data upon which behavioral analysis is performed by the secondary monitoring network.

18. The IC of claim 9, wherein the specified number of packets represents an expected number of IP packets passing over an interface during a particular duration of time.

19. A device comprising:

an integrated circuit (“

IC”

) comprising;

a primary routing network for performing a plurality of operations that implement a user design, the primary routing network comprising a plurality of configurable circuits; and

a secondary monitoring network for receiving a set of data from the primary routing network and performing bandwidth analysis on the set of data, wherein said set of data comprises data that is at least one of (i) input and (ii) output data of a set of circuits of the primary routing network, wherein said secondary monitoring network comprises a network that interpenetrates the primary routing network and is communicatively coupled to a plurality of the circuits of the primary routing network.

20. The device of claim 19, wherein said bandwidth analysis comprises a bandwidth measurement of at least one of Media Access Control (MAC) packets, Transmission Control Protocol Packets (TCP), and Asynchronous Transfer Mode (ATM) packets.

21. The device of claim 19, wherein said bandwidth analysis identifies bottlenecks within the user design while the primary routing network is performing the plurality of operations, wherein the bandwidth analysis identifies the bottlenecks without interfering with the operations of the primary routing network.