Memory device and bit error detection method thereof

• US 8,479,077 B2
• Filed: 05/15/2007
• Issued: 07/02/2013
• Est. Priority Date: 10/24/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Shea-Yun, Song, Dong-Hyun, Kim, Jang-Hwan, Min, Sang-Lyul
• Primary Examiner(s): LAMARRE, GUY J
• Application Number:
  US11/748,933
• Publication Number:
  US 20070226588A1
• Time in Patent Office: 2,240 Days
• Field of Search: 714/758, 714/763, 714/782
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Abstract

A memory device detects and correct bit errors. The memory device includes cyclic redundancy check (CRC) and error correction code (ECC) circuits. The CRC circuit generates a write CRC code corresponding to data to be stored in memory cells. The ECC circuit generates an ECC code corresponding to the data and detecting and correcting a bit error of the data by means of the ECC code during a read operation. The CRC circuit generates a read CRC code corresponding to data corrected by the ECC circuit during the read operation, and detects a bit error of the data according to a comparison of the read CRC code and the write CRC code.

Claims

1. A memory device comprising:

a cyclic redundancy check (CRC) circuit generating a write CRC code corresponding to data to be stored in memory cells; and

an error correction code (ECC) circuit generating an ECC code corresponding to the data and detecting and correcting an error of the data by means of the ECC code during a read operation,

wherein the CRC circuit generates a read CRC code corresponding to data corrected by the ECC circuit during the read operation, and detects an error of the data not corrected by the ECC circuit according to a comparison of the read CRC code and the write CRC code.

2. The memory device as set forth in claim 1, wherein the CRC circuit generates a pass signal when the read CRC code matches the write CRC code and generates a fail signal when the read CRC code does not match the write CRC code.

3. The memory device as set forth in claim 1, wherein the CRC circuit comprises:

a CRC engine receiving the data corrected by the ECC circuit and generating the read CRC code; and

a comparator generating the pass signal when the read CRC code matches with the write CRC code, and generating the fail signal when the read CRC code does not match the write CRC code.

4. The memory device as set forth in claim 1, wherein the memory device is a NAND flash memory device comprising a cell array divided into main and spare regions, and

wherein the data is programmed into the main region and the ECC and CRC codes are programmed into the spare region.

5. The memory device as set forth in claim 4, wherein the ECC circuit detects two error bits and corrects one error bit, and

wherein the CRC circuit detects more than two error bits.

6. A memory device comprising:

a cyclic redundancy check (CRC) circuit generating a write CRC code corresponding to data to be stored in memory cells;

a first error correction code (ECC) circuit generating a first ECC code corresponding to the data and detecting and correcting an error of the data by means of the first ECC code during a read operation; and

a second ECC circuit generating a second ECC code corresponding to the write CRC code and detecting and correcting an error of the write CRC code by means of the second ECC code during the read operation,

wherein the CRC circuit generates a read CRC code corresponding to data corrected by the first ECC circuit during the read operation, and detects an error of the data not corrected by the ECC circuit according to a comparison of the read CRC code and the write CRC code corrected by the second ECC circuit.

7. The memory device as set forth in claim 6, wherein the CRC circuit generates a pass signal when the read CRC code matches the corrected write CRC code, and generates a fail signal when the read CRC code does not match the corrected write CRC code.

8. The memory device as set forth in claim 6, wherein the CRC circuit comprises:

a CRC engine receiving the data corrected by the first ECC circuit and generating the read CRC code; and

a comparator generating the pass signal when the read CRC code matches the corrected write CRC code, and generating the fail signal when the read CRC code does not match the corrected write CRC code.

9. The memory device as set forth in claim 6, wherein the memory device is a NAND flash memory device that has a cell array divided into main and spare regions, and

wherein the data is programmed into the main region and the first and second ECC codes and the CRC code are programmed into the spare region.

10. The memory device as set forth in claim 9, wherein the first and second ECC circuits each detect two error bits and correct one error bit, and

wherein the CRC circuit detects more than two error bits.

11. The memory device as set forth in claim 9, wherein the data, the first and second ECC codes, and the CRC code are programmed substantially simultaneously.

12. A method of detecting an error in a memory device, comprising:

generating, by an ECC circuit, error correction code (ECC) and cyclic redundancy check (CRC) codes corresponding to data to be stored in memory cells;

storing the data in the memory cells;

generating corrected data by correcting an error for the data stored in the memory cells by utilizing the ECC code;

generating, by a CRC circuit, a read CRC code corresponding to the corrected data; and

detecting an error of the corrected data not corrected by the ECC circuit according to a comparison of the read CRC code to the write CRC code.

13. The method as set forth in claim 12, wherein correcting the error comprises treating the data as being failed when the number of error bits is over a correctable number of error bits.

14. The method as set forth in claim 12, further comprising determining a failure of the data when the read CRC code does not match the write CRC code.

15. The method as set forth in claim 12, wherein the memory device is a NAND flash memory device comprising a cell array divided into main and spare regions,

the method further comprising programming the data into the main region and programming the ECC and CRC codes into the spare region.

16. The method as set forth in claim 15, wherein correcting the error comprises detecting first and second error bits and correcting the first error bit, and

wherein detecting the error of the corrected data comprises determining the second error bit in the corrected data.

17. A method of detecting an error in a memory device, comprising:

generating, by a CRC circuit, a write cyclic redundancy check (CRC) code corresponding to data to be stored in memory cells;

generating, by a first ECC circuit, a first error correction code (ECC) code corresponding to the data to be stored in the memory cells, and a second ECC code, by a second ECC circuit, corresponding to the write CRC code;

programming the data, the write CRC code, and the first and second ECC codes into the memory cells;

generating corrected data by correcting an error of the data by means of the first ECC code

generating corrected write CRC code by correcting an error of the write CRC code by means of the second ECC code;

generating a read CRC code corresponding to the corrected data; and

detecting, by the CRC circuit, an error of the corrected data not corrected by the ECC circuits according to a comparison of the read CRC code and the corrected write CRC code.

18. The method as set forth in claim 17, wherein correcting the error of the data by means of the first ECC code further comprises treating the data as being failed when the number of error bits is over a correctable number of error bits.

19. The method as set forth in claim 17, wherein the memory device is a NAND flash memory device comprising a cell array divided into main and spare regions, and

the method further comprising programmed the data into the main region, and the first ECC codes, the second ECC codes, and the CRC code are programmed into the spare region.

20. The method as set forth in claim 19, wherein correcting the error of the data by means of the first ECC code comprises detecting first and second error bits and correcting the first error bit, and

wherein detecting, by the CRC circuit, the error of the corrected data further comprises determining the second error bit in the corrected data.