Automatically creating vias in a circuit design

• US 8,479,140 B2
• Filed: 12/22/2011
• Issued: 07/02/2013
• Est. Priority Date: 07/25/2007
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: AWR Corporation
• Inventors: Pekarek, Joseph Edward
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US13/334,812
• Publication Number:
  US 20120131534A1
• Time in Patent Office: 558 Days
• Field of Search: 716118-119, 716122-132, 716134-135, 716/110, 716137-138
• US Class Current: 716/126
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Creating and detecting crossings of conductive traces on different layers of an integrated circuit or a conducting trace over a device contact in a system. Values are stored by a system simulator corresponding to a galvanic potential or same “net”. According to a set of rule based instructions vias are automatically displayed, correct-by-construction, and via connections between the traces, or the trace and device contact, to short circuit the paths. The via structure will not be created if it will short-circuit a conducting trace not associated with the net in question. By connecting traces on different layers using automatically created via structures so as not to short circuit other net traces, errors are eliminated and design cycles reduced when compared to a manual design scheme of inserting via connections. There is an interactive mode which allows the via to be easily resized by the use of familiar control handles.

Claims

1. A non-transitory computer-readable memory medium that stores program instructions executable by a processor to:

determine an overlap area between at least two circuit components in a layout representation of a circuit design, wherein the circuit design comprises information regarding allocation of nets to circuit components in a schematic representation of the circuit design, and wherein the at least two circuit components are part of a first net in the schematic representation of the circuit design; and

automatically insert a conducting via in the overlap area between the at least two circuit components in the layout representation of the circuit design, based on the information regarding allocation of nets in the schematic representation of the circuit design, wherein the conducting via connects at least two layers in the layout representation of the circuit design without the at least two layers having previously been identified as needing to be connected to each other in the overlap area.

2. The non-transitory computer-readable memory medium of claim 1, wherein the circuit components comprise metallization layers.

3. The non-transitory computer-readable memory medium of claim 1, wherein the circuit components comprise device pins.

4. The non-transitory computer-readable memory medium of claim 1, wherein the program instructions are further executable to perform:

resizing the conducting via size in response to user input to user control handles associated with the conducting via.

5. The non-transitory computer-readable memory medium of claim 1, wherein the overlap area comprises an overlap between the at least two layers.

6. The non-transitory computer-readable memory medium of claim 1, wherein the program instructions are further executable to perform:

setting the conducting via size by limiting the conducting via to the overlap area of the circuit component with the conducting via.

7. The non-transitory computer-readable memory medium of claim 1, wherein the program instructions are further executable to perform:

setting the conducting via size by extending the conducting via to extend beyond the overlap area of the circuit component with the conducting via.

8. The non-transitory computer-readable memory medium of claim 1, wherein the program instructions are further executable to perform:

creating a via cap capable of supporting a plurality of conducting vias.

9. The non-transitory computer-readable memory medium of claim 1, wherein the program instructions are further executable to perform:

setting the conducting via size by encompassing the area bounded by an overlap of the at least two circuit components with the conducting via.

10. The non-transitory computer-readable memory medium of claim 1, wherein the conducting via is automatically created between a first metal trace located on a first layer and a second metal trace located on a second layer.

11. The non-transitory computer-readable memory medium of claim 10, wherein the conducting via has a wider width than the first and second metal traces.

12. The non-transitory computer-readable memory medium of claim 1, wherein the program instructions are further executable to perform:

creating user defined construction constraints to limit the resizing of the conducting via.

13. A computer-implemented method for automatically generating electrical connections between circuit components in a circuit design, the method comprising:

utilizing a computer to perform;

determining an overlap area between at least two circuit components in a layout representation of the circuit design, wherein the circuit design comprises information regarding allocation of nets to circuit components in a schematic representation of the circuit design, and wherein the at least two circuit components are part of a first net in the schematic representation of the circuit design; and

automatically inserting a conducting via in the overlap area between the at least two circuit components in the layout representation of the circuit design, based on the information regarding allocation of nets in the schematic representation of the circuit design, wherein the conducting via connects at least two layers in the layout representation of the circuit design without the at least two layers having previously been identified as needing to be connected to each other in the overlap area.

14. A non-transitory computer-readable memory medium that stores program instructions executable by a processor to perform:

determining an overlap area between at least two circuit components in the circuit design, wherein the circuit design comprises information regarding allocation of nets to circuit components in the circuit design, and wherein the at least two circuit components are part of a first net and have no other circuit components connected to a different net located in the overlap area between the at least two circuit components; and

automatically inserting a conducting via structure in the circuit design based on user defined design rules and the information regarding allocation of nets to circuit components in the circuit design, wherein the conducting via structure comprises a plurality of vias and a via cap in the overlap area between the at least two circuit components, wherein the plurality of vias connect at least two layers in the circuit design.

15. The non-transitory computer-readable memory medium of claim 14, wherein the via cap is larger in cross sectional area than the plurality of vias.

16. The non-transitory computer-readable memory medium of claim 14, wherein the circuit components further comprise metallization layers.

17. The non-transitory computer-readable memory medium of claim 14, wherein the circuit components further comprise device pins.

18. The non-transitory computer-readable memory medium of claim 17, wherein the program instructions are further executable to perform:

setting the conducting via structure size by encompassing an area bounded by the overlapping area of a device pin with the conducting via structure.

19. The non-transitory computer-readable memory medium of claim 14, wherein the program instructions are further executable to perform:

creating a layout for a circuit board based on the circuit design, wherein the automatically inserted conducting via structure electrically connects at least two circuit layers.

20. The non-transitory computer-readable memory medium of claim 14, wherein the program instructions are further executable to perform:

creating a layout for an integrated circuit based on the circuit design, wherein the automatically inserted conducting via structure electrically connects at least two circuit layers.

21. The non-transitory computer-readable memory medium of claim 14, wherein the program instructions are further executable to perform:

resizing the conducting via structure size in response to user input to user control handles associated with the conducting via structure.

22. The non-transitory computer-readable memory medium of claim 14, wherein the program instructions are further executable to perform:

setting the conducting via structure size by limiting the conducting via structure to the overlap area of the at least two circuit components with the conducting via structure.

23. The non-transitory computer-readable memory medium of claim 14, wherein the program instructions are further executable to perform:

setting the conducting via structure size by extending the conducting via structure beyond the overlap area of the at least two circuit components with the conducting via structure.

24. The non-transitory computer-readable memory medium of claim 14, wherein the program instructions are further executable to perform:

creating the conducting via structure in the shape of a polygon.

25. The non-transitory computer-readable memory medium of claim 24, wherein the program instructions are further executable to perform:

resizing the conducting via structure in response to user input to one or more user control handles associated with the conducting via structure.

26. The non-transitory computer-readable memory medium of claim 25, wherein the program instructions are further executable to perform:

implementing construction constraints to limit the conducting via structure size.

27. A computer-implemented method for automatically generating electrical connections between circuit components in a circuit design, the method comprising:

utilizing a computer to perform;

determining an overlap area between at least two circuit components in the circuit design, wherein the circuit design comprises information regarding allocation of nets to circuit components in the circuit design, and wherein the at least two circuit components are part of a first net and have no other circuit components connected to a different net located in the overlap area between the at least two circuit components; and

automatically inserting a conducting via structure in the circuit design based on user defined design rules and the information regarding allocation of nets to circuit components in the circuit design, wherein the conducting via structure comprises a plurality of vias and a via cap in the overlap area between the at least two circuit components, wherein the plurality of vias connect at least two layers in the circuit design.

28. A non-transitory computer-readable memory medium that stores program instructions executable by a processor to perform:

determining that a plurality of metallic conducting traces comprised in two or more layers of a circuit design overlap, wherein the circuit design comprises information indicating that the plurality of metallic conducting traces are part of a first net;

determining whether there are no traces of other nets in the overlap of the plurality of metallic conducting traces;

determining whether a conducting via can automatically be created in the overlap between the plurality of metallic conducting traces in response to determining that there are no traces of other nets in the overlap of the plurality of metallic conducting traces; and

inserting at least one conducting via in the overlap between the plurality of metallic conducting traces in response to determining that the conducting via can be automatically created in the overlap, wherein said inserting is based on the information indicating that the plurality of metallic conducting traces are part of the first net.

29. The non-transitory computer-readable memory medium of claim 28, wherein the program instructions are further executable to perform:

resizing the at least one conducting via in response to user input to one or more control handles associated with the at least one conducting via.