Automation using spine routing

• US 8,479,141 B1
• Filed: 01/17/2012
• Issued: 07/02/2013
• Est. Priority Date: 06/07/2004
• Status: Active Grant

• Current Assignee: Pulsic Limited
• Original Assignee: Pulsic Limited
• Inventors: Waller, Mark, Parker, Tim, Williams, Mark, Birch, Jeremy, Balsdon, Graham, Sato, Fumiako
• Primary Examiner(s): Parihar, Suchin
• Application Number:
  US13/352,232
• Time in Patent Office: 532 Days
• Field of Search: 716/100, 716/126
• US Class Current: 716/126
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.

Claims

1. A method comprising:

providing N pins to couple together using a net;

finding a rectangular route region, comprising the N pins, having a length greater than a width, wherein the length is in a first direction and the width is a second direction, orthogonal to the first direction;

using at least one computer processor, in the rectangular route region, placing a first spine interconnect extending in the first direction at a position in the second direction based on a quotient of a sum of the positions of the N pins in the second direction and N; and

routing N stitching interconnects in the second direction to couple each of the N pins to the first spine interconnect.

2. The method of claim 1 wherein the first spine interconnect and N stitching interconnects forms a first interconnect track and the method further comprises:

providing M pins to couple together using a net;

in the rectangular route region, placing a second spine interconnect extending in the first direction at a position in the second direction based on a weighted average of positions of the M pins; and

routing M stitching interconnects in the second direction to couple each of the M pins to the second spine interconnect, wherein the second spine interconnect and M stitching interconnects forms a second interconnect track.

3. The method of claim 2 further comprising:

lengthening the second interconnect track in order to match timing delays of the first and second interconnect tracks.

4. The method of claim 2 further comprising:

increasing a space between the first and second interconnect track in order to match timing delays of the first and second interconnect track.

5. The method of claim 1 further comprising:

placing a first shield interconnect adjacent to the first spine interconnect on a first side.

6. The method of claim 5 further comprising:

placing a second shield interconnect adjacent to the first spine interconnect on a second side.

7. The method of claim 2 further comprising:

placing a first shield interconnect adjacent to the first spine interconnect on a first side; and

placing a second shield interconnect adjacent to the first spine interconnect, between the first spine interconnect and the second spine interconnect.

8. The method of claim 2 further comprising:

placing a first shield interconnect adjacent to the first spine interconnect on a first side; and

placing a second shield interconnect adjacent to the second spine interconnect, wherein the first and second spine interconnects are between the first and second shield interconnects.

9. A method for routing at least one interconnect of an integrated circuit comprising:

identifying N pins to couple;

calculating a rectangular route area to comprise the positions in a first direction of the N pins;

determining if at least one forbidden area is located within the route area;

using at least one computer processor, routing outside of the at least one forbidden area a spine interconnect extending in the first direction an entire length of the route area in the first direction; and

routing N stitching interconnects in a second direction to couple each of the N pins to the spine interconnect,

wherein the at least one forbidden area being a rectangular area to include at least one obstacle and extend in the first direction an entire length of the route area in the first direction,

the first direction is orthogonal to the second direction, and

the route area in the second direction extends between the most oppositely disposed in the second direction of the at least two pins.

10. A method for routing at least one interconnect of an integrated circuit comprising:

identifying N pins to couple;

calculating a rectangular route area to comprise the positions in a first direction of the N pins;

determining if at least one forbidden area is located within the route area;

using at least one computer processor, routing outside of the at least one forbidden area a spine interconnect extending in the first direction an entire length of the route area in the first direction;

routing N stitching interconnects in a second direction to couple each of the N pins to the spine interconnect,

wherein the at least one forbidden area being a rectangular area to include at least one obstacle and extend in the first direction an entire length of the route area in the first direction, and

the first direction is orthogonal to the second direction; and

determining a position in the second direction for the spine interconnect to reduce an average length of the plurality of stitching interconnects.

11. A method for routing at least one interconnect of an integrated circuit comprising:

identifying N pins to couple;

calculating a rectangular route area to comprise the positions in a first direction of the N pins;

determining if at least one forbidden area is located within the route area;

using at least one computer processor, routing outside of the at least one forbidden area a spine interconnect extending in the first direction an entire length of the route area in the first direction; and

routing N stitching interconnects in a second direction to couple each of the N pins to the spine interconnect,

wherein the at least one forbidden area being a rectangular area to include at least one obstacle and extend in the first direction an entire length of the route area in the first direction, and

the first direction is orthogonal to the second direction, and

the position of the spine interconnect in the second direction being a quotient of the sum of the positions of the N pins in the second direction and N.

12. A method for routing at least one interconnect of an integrated circuit comprising:

identifying N pins to couple;

calculating a rectangular route area to comprise the positions in a first direction of the N pins;

determining if at least one forbidden area is located within the route area;

using at least one computer processor, routing outside of the at least one forbidden area a spine interconnect extending in the first direction an entire length of the route area in the first direction; and

routing N stitching interconnects in a second direction to couple each of the N pins to the spine interconnect,

wherein the at least one forbidden area being a rectangular area to include at least one obstacle and extend in the first direction an entire length of the route area in the first direction, and

the first direction is orthogonal to the second direction, and

the position of the spine interconnect in the second direction is a closest position outside the at least one forbidden area to a weighted average position in the second direction of the at least two pins positions.

13. A method for routing at least one interconnect of an integrated circuit comprising:

identifying N pins to couple;

calculating a rectangular route area to comprise the positions in a first direction of the N pins;

determining if at least one forbidden area is located within the route area;

using at least one computer processor, routing outside of the at least one forbidden area a spine interconnect extending in the first direction an entire length of the route area in the first direction; and

routing N stitching interconnects in a second direction to couple each of the N pins to the spine interconnect,

wherein the at least one forbidden area being a rectangular area to include at least one obstacle and extend in the first direction an entire length of the route area in the first direction,

the first direction is orthogonal to the second direction; and

determining if a path of each of the plurality of stitching interconnects is unobstructed by the at least one obstacle.

14. A method for routing at least one interconnect of an integrated circuit comprising:

identifying N pins to couple;

calculating a rectangular route area to comprise the positions in a first direction of the N pins;

determining if at least one forbidden area is located within the route area;

using at least one computer processor, routing outside of the at least one forbidden area a spine interconnect extending in the first direction an entire length of the route area in the first direction; and

routing N stitching interconnects in a second direction to couple each of the N pins to the spine interconnect,

wherein the at least one forbidden area being a rectangular area to include at least one obstacle and extend in the first direction an entire length of the route area in the first direction,

the first direction is orthogonal to the second direction, and

an edge of the route area being an edge of a chip, the edge of the chip includes one of the at least one pins.

15. A method comprising:

providing a routing area having a length dimension greater than a width dimension, wherein the routing area comprises a plurality of first pins to be coupled together using a first interconnect, and a plurality of second pins to be coupled together using a second interconnect;

using at least one computer processor, within the routing area, generating a first spine polygon of the first interconnect having a plurality of straight edges extending the length of the routing area and a uniform first width between the straight edges;

within the routing area, generating a second spine polygon of the second interconnect, parallel to the first spine polygon, having a plurality of straight edges extending the length of the routing area and the uniform first width between the straight edges;

generating a first plurality of stitch polygons to couple each of the first pins to the first polygon; and

generating a second plurality of stitch polygons to couple each of the second pins to the second polygon,

wherein a length-to-width ratio of the routing area is at least four-to-one.

16. A method comprising:

providing a routing area having a length dimension greater than a width dimension, wherein the routing area comprises a plurality of first pins to be coupled together using a first interconnect, and a plurality of second pins to be coupled together using a second interconnect;

using at least one computer processor, within the routing area, generating a first spine polygon of the first interconnect having a plurality of straight edges extending the length of the routing area and a uniform first width between the straight edges;

within the routing area, generating a second spine polygon of the second interconnect, parallel to the first spine polygon, having a plurality of straight edges extending the length of the routing area and the uniform first width between the straight edges;

generating a first plurality of stitch polygons to couple each of the first pins to the first polygon; and

generating a second plurality of stitch polygons to couple each of the second pins to the second polygon,

wherein at least one of the stitch polygons has a length greater than its width, and its length is perpendicular to the length of the spine polygons.

17. A method comprising:

providing a routing area having a length dimension greater than a width dimension, wherein the routing area comprises a plurality of first pins to be coupled together using a first interconnect, and a plurality of second pins to be coupled together using a second interconnect;

using at least one computer processor, within the routing area, generating a first spine polygon of the first interconnect having a plurality of straight edges extending the length of the routing area and a uniform first width between the straight edges;

within the routing area, generating a second spine polygon of the second interconnect, parallel to the first spine polygon, having a plurality of straight edges extending the length of the routing area and the uniform first width between the straight edges;

generating a first plurality of stitch polygons to couple each of the first pins to the first polygon; and

generating a second plurality of stitch polygons to couple each of the second pins to the second polygon,

wherein the routing area comprises an obstacle polygon and generating a first plurality of stitch polygons to couple each of the first pins to the first polygon comprises;

performing one or more flood operations to route at least one of the stitch polygons around the obstacle.

18. A method comprising:

providing a routing area having a length dimension greater than a width dimension, wherein the routing area comprises a plurality of first pins to be coupled together using a first interconnect, and a plurality of second pins to be coupled together using a second interconnect;

using at least one computer processor, within the routing area, generating a first spine polygon of the first interconnect having a plurality of straight edges extending the length of the routing area and a uniform first width between the straight edges;

within the routing area, generating a second spine polygon of the second interconnect, parallel to the first spine polygon, having a plurality of straight edges extending the length of the routing area and the uniform first width between the straight edges;

generating a first plurality of stitch polygons to couple each of the first pins to the first polygon;

generating a second plurality of stitch polygons to couple each of the second pins to the second polygon; and

providing a forbidden area within the routing area, wherein the first and second spine polygons are positioned within the routing area and outside the forbidden area.