Semiconductor element comprising a low variation substrate diode

• US 8,481,374 B2
• Filed: 10/28/2010
• Issued: 07/09/2013
• Est. Priority Date: 01/29/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Scheiper, Thilo
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): KUSUMAKAR, KAREN M
• Application Number:
  US12/914,123
• Publication Number:
  US 20110186957A1
• Time in Patent Office: 985 Days
• Field of Search: 438149-166, 257506-510, 257347-363
• US Class Current: 438/156
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits

Abstract

A substrate diode of an SOI device may be formed on the basis of contact regions in an early manufacturing stage, i.e., prior to patterning gate electrode structures of transistors, thereby imparting superior stability to the sensitive diode regions, such as the PN junction. In some illustrative embodiments, only one additional deposition step may be required compared to conventional strategies, thereby providing a very efficient overall process flow.

Claims

1. A method of forming a substrate diode in a semiconductor device, the method comprising:

forming a well region of said substrate diode in a crystalline material of a substrate of said semiconductor device;

forming a first opening through a first trench isolation structure and a second opening through a second trench isolation structure after forming the well region, said first and second openings extending through a buried insulating layer of said semiconductor device so as to expose a portion of the well region

filling said first and second openings with a conductive material so as to provide a first contact region and a second contact region of said substrate diode;

forming a PN junction of said substrate diode on the basis of the well region and said conductive material formed in said first opening;

forming a circuit element in and above an active region after filling said first and second openings with said conductive material;

forming an interlayer dielectric material above said active region and said first and second contact regions; and

forming contact elements in said interlayer dielectric material so as to connect to said circuit element and to said first and second contact regions of said substrate diode.

2. The method of claim 1, wherein said conductive material comprises a semiconductor material.

3. The method of claim 1, wherein said conductive material comprises carbon.

4. The method of claim 1, wherein forming said conductive material comprises depositing said conductive material as an in situ doped material.

5. The method of claim 1, wherein forming said first and second openings comprises providing active regions laterally adjacent to each of said first and second trench isolation structures and using a hard mask formed on said active regions as an etch mask.

6. The method of claim 5, further comprising removing said hard mask and excess material of said conductive material by performing a polishing process.

7. The method of claim 1, further comprising forming the well region of said substrate diode in said crystalline material by using a mask having formed therein a first mask opening and a second mask opening.

8. The method of claim 7, wherein said first and second openings are formed by using said mask after forming the well region.

9. The method of claim 1, wherein forming said PN junction comprises introducing a dopant species of a first conductivity type into said first contact region and a dopant species of an inverse conductivity type into said second contact region and initiating dopant diffusion by performing an anneal process.

10. A method of forming a substrate diode of a semiconductor device, said method comprising:

forming a well region in a crystalline substrate material of said semiconductor device by implanting a well dopant species through at least a buried insulating layer formed between said crystalline substrate material and a device layer comprising a plurality of active regions and a plurality of isolation structures;

forming a first opening and a second opening after forming the well region, wherein the first and second openings extend through an insulating material of at least one of said isolation structures and through said buried insulating material to expose the well region;

filling said first and second openings with a conductive material; and

forming a transistor in said device layer after filling said first and second openings with a conductive material.

11. The method of claim 10, wherein said well region and said first and second openings are formed by using the same mask layer formed above said device layer.

12. The method of claim 11, wherein forming said first and second openings further comprises using said mask and a hard mask material formed on said plurality of active regions as an etch mask.

13. The method of claim 10, wherein filling said first and second openings comprises forming a semiconductor material in said first and second openings.

14. The method of claim 10, wherein filling said first and second openings comprises forming a carbon comprising material in said first and second openings.

15. The method of claim 10, wherein filling said first and second openings comprises forming an in situ doped material in said first and second openings.

16. The method of claim 10, further comprising forming an interlayer dielectric material above said device layer and forming contact elements in said interlayer dielectric material so as to connect to said circuit element and said first and second contact regions of said substrate diode.

17. The method of claim 10, further comprising forming a PN junction of said substrate diode by initiating an interdiffusion of said well dopant species and an inverse dopant species provided in said conductive material formed in said first opening.