Method for manufacturing a semiconductor device with impurity doped oxide semiconductor
First Claim
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1. A method for manufacturing a semiconductor device, comprising the steps of:
- forming an oxide semiconductor layer over an insulating surface;
forming a source electrode layer and a drain electrode layer over and partly in contact with the oxide semiconductor layer;
forming an insulating layer over and in contact with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer;
forming a gate electrode over the insulating layer and overlapping with the oxide semiconductor layer; and
adding an impurity element to a part of the oxide semiconductor layer in a self-alignment manner with the use of the gate electrode, the source electrode layer and the drain electrode layer as a mask through the insulating layer,wherein the impurity element is a rare gas.
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Abstract
It is an object to provide a semiconductor device including an oxide semiconductor, in which miniaturization of a transistor is achieved and the concentration of an electric field is relieved. The width of a gate electrode is reduced and a space between a source electrode layer and a drain electrode layer is shortened. By adding a rare gas in a self-alignment manner with the use of a gate electrode as a mask, a low-resistance region in contact with a channel formation region can be provided in an oxide semiconductor layer. Accordingly, even when the width of the gate electrode, that is, the line width of a gate wiring is small, the low-resistance region can be provided with high positional accuracy, so that miniaturization of a transistor can be realized.
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Citations
18 Claims
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1. A method for manufacturing a semiconductor device, comprising the steps of:
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forming an oxide semiconductor layer over an insulating surface; forming a source electrode layer and a drain electrode layer over and partly in contact with the oxide semiconductor layer; forming an insulating layer over and in contact with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; forming a gate electrode over the insulating layer and overlapping with the oxide semiconductor layer; and adding an impurity element to a part of the oxide semiconductor layer in a self-alignment manner with the use of the gate electrode, the source electrode layer and the drain electrode layer as a mask through the insulating layer, wherein the impurity element is a rare gas. - View Dependent Claims (2, 3, 4, 5)
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6. A method for manufacturing a semiconductor device, comprising the steps of:
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forming a source electrode layer and a drain electrode layer over an insulating surface; forming an oxide semiconductor layer over and partly in contact with the source electrode layer and the drain electrode layer; forming an insulating layer over and in contact with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; forming a gate electrode over and in contact with the insulating layer; and adding an impurity element to a part of the oxide semiconductor layer in a self-alignment manner with the use of the gate electrode as a mask through the insulating layer, wherein the gate electrode overlaps with the oxide semiconductor layer, and wherein the impurity element is a rare gas. - View Dependent Claims (7, 8, 9, 10)
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11. A method for manufacturing a semiconductor device, comprising the steps of:
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forming an oxide semiconductor layer over an insulating surface; forming a source electrode layer and a drain electrode layer over and partly in contact with the oxide semiconductor layer; forming an insulating layer over and in contact with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; forming a gate electrode over the insulating layer and overlapping with the oxide semiconductor layer; etching the insulating layer selectively so that a part of the oxide semiconductor layer is exposed; and adding an impurity element to the exposed part of the oxide semiconductor layer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsAkimoto, Kengo, Watanabe, Ryosuke, Tsubuku, Masashi, Yamazaki, Shunpei
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Primary Examiner(s)Montalvo, Eva Y
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Application NumberUS13/026,518Publication NumberTime in Patent Office876 DaysField of Search438/149, 438/151, 438/161, 438/181, 257/43US Class Current438/181CPC Class CodesH01L 29/41733 for thin film transistors w...H01L 29/66969 of devices having semicondu...H01L 29/78618 characterised by the drain ...H01L 29/7869 having a semiconductor body...
