Methods of fabricating a memory device

• US 8,481,385 B2
• Filed: 05/11/2012
• Issued: 07/09/2013
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gordon, Haller A., Sanh, Tang D., Steven, Cummings
• Primary Examiner(s): Menz, Douglas M
• Assistant Examiner(s): PRASAD, NEIL R
• Application Number:
  US13/469,513
• Publication Number:
  US 20120231592A1
• Time in Patent Office: 424 Days
• Field of Search: 438/242, 438/288, 438/972, 438/253, 257/E21.646
• US Class Current: 438/253
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

Claims

1. A method of fabricating a memory device, the method comprising;

forming a recessed gate within semiconductive material;

forming a first source/drain region and a second source/drain region adjacent opposing lateral sides of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is within the semiconductive material;

forming a charge storage device above the semiconductive material, wherein the charge storage device is electrically coupled to the first source/drain region; and

forming a conductive data line which electrically and directly physically contacts the second source/drain region in the absence of any separately formed conductive plug extending between the second source/drain region and the conductive data line in a completed construction of the memory device.

2. The method of claim 1 comprising forming the first and second source/drain regions to have coplanar upper surfaces in the completed construction of the memory device.

3. The method of claim 1 comprising forming the charge storage device to comprise a capacitor.

4. The method of claim 3 comprising forming the capacitor to comprise:

a storage node;

a dielectric substantially surrounding the storage node; and

a top cell plate substantially surrounding the dielectric.

5. The method of claim 1 comprising forming an upper surface of the gate to be elevationally below upper surfaces of each of the first and second source/drain regions.

6. The method of claim 5 comprising forming the upper surface of the gate to be elevationally closer to a lower surface of the second source/drain region than to the second source/drain region upper surface in the completed construction of the memory device.

7. The method of claim 1 comprising forming an upper surface of the gate to be elevationally closer to lower surfaces of each of the first and second source/drain regions than to an upper surface of the semiconductive material in the completed construction of the memory device.

8. The method of claim 2 comprising forming a gate dielectric in contact with the recessed gate and to extend along the lateral sides, and forming the gate dielectric to have an uppermost surface which is co-planar with the upper surfaces of each of the first and second source/drain regions in the completed construction of the memory device.

9. A method of fabricating a memory device, the method comprising;

forming a recessed gate within semiconductive material;

forming a first source/drain region and a second source/drain region adjacent opposing lateral sides of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is within the semiconductive material;

forming a charge storage device above the semiconductive material, wherein the charge storage device is electrically coupled to the first source/drain region;

forming a conductive data line electrically coupled to the second source/drain region; and

forming the first and second source/drain regions to have coplanar upper surfaces in a completed construction of the memory device.

10. A method of fabricating a memory device, the method comprising;

forming a recessed gate within semiconductive material;

forming a first source/drain region and a second source/drain region adjacent opposing lateral sides of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is within the semiconductive material;

forming a charge storage device above the semiconductive material, wherein the charge storage device is electrically coupled to the first source/drain region;

forming a conductive data line electrically coupled to the second source/drain region;

forming an upper surface of the gate to be elevationally below upper surfaces of each of the first and second source/drain regions; and

forming the upper surface of the gate to be elevationally closer to a lower surface of the second source/drain region than to the second source/drain region upper surface in a completed construction of the memory device.

11. A method of fabricating a memory device, the method comprising;

forming a recessed gate within semiconductive material;

forming a first source/drain region and a second source/drain region adjacent opposing lateral sides of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is within the semiconductive material;

forming a charge storage device above the semiconductive material, wherein the charge storage device is electrically coupled to the first source/drain region;

forming a conductive data line electrically coupled to the second source/drain region; and

forming an upper surface of the gate to be elevationally closer to lower surfaces of each of the first and second source/drain regions than to an upper surface of the semiconductive material in a completed construction of the memory device.

12. A method of fabricating a memory device, the method comprising;

forming a recessed gate within semiconductive material;

forming a first source/drain region and a second source/drain region adjacent opposing lateral sides of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is within the semiconductive material;

forming a charge storage device above the semiconductive material, wherein the charge storage device is electrically coupled to the first source/drain region;

forming a conductive data line electrically coupled to the second source/drain region;

forming a gate dielectric in contact with the recessed gate and to extend along the lateral sides; and

forming the gate dielectric to have an uppermost surface which is co-planar with upper surfaces of each of the first and second source/drain regions in a completed construction of the memory device.