Self-aligned contact combined with a replacement metal gate/high-K gate dielectric

• US 8,481,415 B2
• Filed: 12/02/2010
• Issued: 07/09/2013
• Est. Priority Date: 12/02/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Yuan, Jun, Guo, Dechao, Wong, Kwong Hon, Wang, Yanfeng, Wang, Gan
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US12/958,608
• Publication Number:
  US 20120139062A1
• Time in Patent Office: 950 Days
• Field of Search: 438585-586, 438/183
• US Class Current: 438/585
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A method of forming a semiconductor device is provided that includes forming a replacement gate structure on portion a substrate, wherein source regions and drain regions are formed on opposing sides of the portion of the substrate that the replacement gate structure is formed on. An intralevel dielectric is formed on the substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the substrate. A high-k dielectric spacer is formed on sidewalls of the opening, and a gate dielectric is formed on the exposed portion of the substrate. Contacts are formed through the intralevel dielectric layer to at least one of the source region and the drain region, wherein the etch that provides the opening for the contacts is selective to the high-k dielectric spacer and the high-k dielectric capping layer.

Claims

1. A method of forming a semiconductor device comprising:

forming a replacement gate structure on a portion of a substrate, wherein source regions and drain regions are formed in opposing sides of the portion of the substrate that the replacement gate structure is formed on;

forming an intralevel dielectric on the substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure;

removing the replacement gate structure to provide an opening to an exposed portion of the substrate;

forming a high-k dielectric spacer on sidewalls of the opening;

forming a gate dielectric on the exposed portion of the substrate;

forming a functioning gate structure within the opening on the gate dielectric, wherein an upper surface of the functioning gate structure is a high-k dielectric capping layer;

and

forming contact vias through the interlevel dielectric layer to at least one of the source region and the drain region, wherein an etch that provides the opening for the contact via is selective to the high-k dielectric spacer and the high-k dielectric capping layer.

2. The method of claim 1, wherein the functioning gate structure includes a work function metal layer that is present on the gate dielectric.

3. The method of claim 1, wherein prior to forming the intralevel dielectric layer, low-k dielectric spacers are formed adjacent to the replacement gate structure.

4. The method of claim 3, wherein the forming of the intralevel dielectric layer on the substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure comprises depositing the intralevel dielectric layer over the substrate and the replacement gate structures, and planarizing the intralevel dielectric layer until the upper surface of the replacement gate structure is exposed.

5. The method of claim 3, wherein the removing of the replacement gate structure to provide an opening to an exposed portion of the substrate comprises an etch that removes the replacement gate structure selective to the low-k dielectric spacer, the substrate and the intralevel dielectric layer.

6. The method of claim 3, wherein the forming of the high-k dielectric spacer on the sidewalls of the opening comprises depositing a conformal high-k dielectric layer on sidewalls of the low-k dielectric spacer that are exposed by removing the replacement gate structure, etching the conformal high-k dielectric layer so that a remaining portion of the conformal high-k dielectric layer is present on the sidewalls of the low-k dielectric spacer, which provide the sidewalls of the opening.

7. The method of claim 3, wherein the forming of the gate dielectric further comprises forming an interfacial dielectric layer on a base portion of the opening, and forming a high-k gate dielectric layer on the interfacial dielectric layer.

8. The method of claim 7, wherein the forming of the work function metal layer on the exposed portion of the substrate comprises depositing titanium aluminum (TiAl) when the semiconductor device is an n-type conductivity semiconductor device or depositing titanium nitride (TiN) when the semiconductor device is a p-type conductivity semiconductor device.

9. The method of claim 3 further comprising forming a metal-containing layer on the work function metal layer filling the opening.

10. The method of claim 9 wherein an upper surface of the metal-containing layer is recessed below an upper surface of the high-k dielectric spacer.

11. The method of claim 10, wherein a high-k dielectric capping layer is formed on the upper surface of the metal-containing layer that has been recessed, wherein the high-k dielectric capping layer in combination with the high-k dielectric spacer encapsulate the work function metal layer and the metal-containing layer.

12. The method of claim 11, wherein the etch for forming the opening through the intralevel dielectric layer for the contact to at the least one of the source region and the drain region is an anisotropic etch that is selective to the high-k dielectric spacer and the high-k dielectric capping layer.

13. A method of forming a complementary metal oxide semiconductor (CMOS) device comprising:

providing a first replacement gate structure within a first device region of a substrate and a second replacement gate structure within a second device region of the substrate, wherein the first device region comprises first source regions and first drain regions of a first conductivity type and the second device region comprises second source regions and second drain regions of a second conductivity type;

forming an intralevel dielectric on the substrate having an upper surface that is coplanar with an upper surface of the first replacement gate structure and the second replacement gate structure;

removing the first replacement gate structure and the second replacement gate structure to provide openings to a first exposed portion of the substrate in the first device region and a second exposed portion of the substrate in a second device region of the substrate;

forming a high-k dielectric spacer on sidewalls of each of the openings to the first exposed portion of the substrate and the second exposed portion of the substrate;

forming a gate dielectric on each of the first exposed portion and the second exposed portion of the substrate;

forming a first work function metal layer on the gate dielectric that is present in the first device region and forming a second work function metal layer on the gate dielectric in the second device region of the substrate;

forming a high-k dielectric capping layer over the first work function metal layer and the second work function metal layer; and

forming contacts through the intralevel dielectric layer to at least one of the source region and the drain region, wherein an etch that provides the opening for the contacts is selective to the high-k dielectric spacer and the high-k dielectric capping layer.

14. The method of claim 13, wherein the first conductivity type is an n-type conductivity and the second conductivity type is a p-type conductivity.

15. The method of claim 14, wherein the first work function metal layer comprises titanium aluminum (TiAl) and the second work function metal layer comprises titanium nitride (TiN).