Low fabrication cost, high performance, high reliability chip scale package

• US 8,481,418 B2
• Filed: 10/31/2007
• Issued: 07/09/2013
• Est. Priority Date: 05/01/2002
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lee, Jin-Yuan, Lei, Ming-Ta, Huang, Ching-Cheng, Lin, Chuen-Jye
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US11/930,220
• Publication Number:
  US 20080113503A1
• Time in Patent Office: 2,078 Days
• Field of Search: 438/613, 438/614, 438/E21.508, 257/737, 257/738, 257/E21.508
• US Class Current: 438/613
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11831 involving a chemical process, e.g. etching the bump connector
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/15 Structure, shape, material or disposition of the bump connectors after the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01084 : Polonium [Po]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H04B 1/7113 : Determination of path profile
• CPC Class Codes: H04B 1/712 : Weighting of fingers for combining, e.g. amplitude control or phase rotation using an inner loop

Abstract

The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

Claims

1. A method for fabricating a circuit component, comprising:

providing a first device comprising semiconductor substrate, a conductive pad over said semiconductor substrate, and a polymer layer over said semiconductor substrate, wherein a first opening in said polymer layer is over a contact point of said conductive pad;

forming a first conductive layer on said contact point of said conductive pad and said polymer layer;

forming a second conductive layer on said first conductive layer;

forming a first photoresist layer over said semiconductor substrate;

electroplating a conductive interconnect in a second opening in said first photoresist layer, wherein said conductive interconnect is coupled to said contact point through said second conductive layer;

forming a nickel-containing layer over said copper conductive interconnect wherein said nickel-containing layer has a width greater than a width of said conductive interconnect;

forming a solder over said nickel-containing layer, in which said solder has a width equal to the width of said nickel-containing layer; and

after said forming said second conductive layer, removing said first conductive layer not under said second conductive layer.

2. The method of claim 1, wherein said polymer layer comprises polyimide.

3. The method of claim 1, wherein said forming said first conductive layer comprises forming a titanium-containing layer over said contact point and said polymer layer.

4. The method of claim 1, wherein said forming said first conductive layer comprises forming a tantalum-containing layer over said contact point and said polymer layer.

5. The method of claim 1 further comprising oxidizing a surface of said conductive interconnect.

6. The method of claim 1, wherein said forming said first conductive layer comprises a sputtering process.

7. The method of claim 1, wherein said forming said second conductive layer comprises an electroplating process.

8. The method of claim 1, after said forming said first conductive layer, further comprising forming a second photoresist layer on said first conductive layer, wherein a third opening in said second photoresist layer exposes a region of said first conductive layer, next said forming said second conductive layer further on said region and in said third opening, and then removing said second photoresist layer.

9. The method of claim 1, whereby an underfill is configured to be between said first device and a second device configured to be bonded with said first device and to contact said first and second devices and a sidewall of said conductive interconnect.

10. The method of claim 1, whereby said second conductive layer has a sidewall not covered by said first conductive layer.

11. A method for fabricating a circuit component, comprising:

providing a first device comprising a semiconductor substrate, a conductive pad over said semiconductor substrate, and a separating layer over said semiconductor substrate, wherein a first opening in said separating layer is over a contact point of said conductive pad;

forming a first conductive layer on said contact point of said conductive pad and over said separating layer;

forming a second conductive layer on said first conductive layer;

electroplating a conductive interconnect in a second opening in a first photoresist layer, in which the conductive interconnect is coupled to said contact point through said second conductive layer;

forming a nickel-containing layer over said conductive interconnect and in said second opening, in which said nickel-containing layer has a width greater than a width of said conductive interconnect;

forming a solder over said nickel-containing layer, in which the solder has a width equal to the width of said nickel-containing layer;

and

removing said first conductive layer not under said second conductive layer, whereby said second conductive layer has a sidewall not covered by said first conductive layer.

12. The method of claim 11, wherein said forming said first conductive layer comprises forming a titanium-containing layer over said contact point and said separating layer.

13. The method of claim 11 wherein said forming said first conductive layer comprises forming a tantalum-containing layer over said contact point and said separating layer.

14. The method of claim 11 further comprising oxidizing a surface of said conductive interconnect.

15. The method of claim 11, wherein said forming said first conductive layer comprises a sputtering process.

16. The method of claim 11, wherein said forming said second conductive layer comprises an electroplating process.

17. The method of claim 11 after said forming said first conductive layer, further comprising forming a second photoresist layer on said first conductive layer, wherein a third opening in said second photoresist layer exposes a region of said first conductive layer, next said forming said second conductive layer further on said region and in said third opening, and then removing said second photoresist layer.

18. A method for fabricating a circuit component, comprising:

providing a first device comprising a semiconductor substrate, a conductive pad over said semiconductor substrate, and a polymer layer over said semiconductor substrate, wherein a first opening in said polymer layer is over a contact point of said conductive pad;

forming a first conductive layer on said contact point of said conductive pad and said polymer layer;

forming a second conductive layer on said first conductive layer;

forming a first photoresist layer over said semiconductor substrate;

electroplating a conductive interconnect in a second opening in said first photoresist layer, in which said conductive interconnect is coupled to said contact point through said second conductive layer;

forming a nickel-containing layer over the conductive interconnect in the second opening, the nickel-containing layer having a width greater than a width of the conductive interconnect;

forming a solder over the nickel-containing layer, in which said solder has a width equal to the width of said nickel-containing layer.

19. The method of claim 18, wherein said polymer layer comprises polymide.

20. The method of claim 18, wherein said forming said first conductive layer comprises forming a titanium-containing layer over said contact point and said polymer layer.

21. The method of claim 18, wherein said forming said first conductive layer comprises forming a tantalum-containing layer over said contact point and said polymer layer.

22. The method of claim 18 further comprising oxidizing a surface of said conductive interconnect.

23. The method of claim 18, wherein said forming said first conductive layer comprises a sputtering process.

24. The method of claim 18, wherein said forming said second conductive layer comprises an electroplating process.

25. The method of claim 18, after said forming said first conductive layer, further comprising forming a second photoresist layer on said first conductive layer, wherein a third opening in said second photoresist layer exposes a region of said first conductive layer, next said forming said second conductive layer further on said region and in said third opening, and then removing said second photoresist layer.

26. The method of claim 18, whereby an underfill is configured to be between said first device and a second device configured to be bonded with said first device and to contact said first and second devices and a sidewall of said conductive interconnect.

27. The method of claim 18, whereby said second conductive layer has a sidewall not covered by said first conductive layer.

28. The method of claim 18 further comprising said forming said solder with a thickness between 10 and 100 micrometers.

29. A method for fabricating a circuit component, comprising:

providing a first device comprising a semiconductor substrate, a conductive pad over said semiconductor substrate, and a separating layer over said semiconductor substrate;

forming a first conductive layer on a contact point of said conductive pad;

forming a second conductive layer on said first conductive layer;

forming a first photoresist layer over said semiconductor substrate;

electroplating a conductive interconnect in an opening in said first photoresist layer, in which said conductive interconnect is coupled to said contact point through said second conductive layer;

forming a gold-containing layer over said conductive interconnect and in said opening;

after said forming said gold-containing layer, removing said first photoresist layer; and

after said forming said second conductive layer, removing said first conductive layer not under said second conductive layer, in which a width of the gold-containing layer is wider than a width of the conductive interconnect.

30. The method of claim 29, wherein said forming said first conductive layer comprises forming a titanium-containing layer over said contact point and said separating layer.

31. The method of claim 29 further comprising oxidizing a surface of said conductive interconnect.

32. The method of claim 29, wherein said forming said first conductive layer comprises a sputtering process.

33. The method of claim 29, wherein said forming said second conductive layer comprises an electroplating process.

34. The method of claim 29, after said forming said first conductive layer, further comprising forming a second photoresist layer on said first conductive layer, wherein a second opening in said second photoresist layer exposes a region of said first conductive layer, next said forming said second conductive layer further on said region and in second opening, and then removing said second photoresist layer.

35. A method for fabricating a circuit component, comprising:

providing a first device comprising a semiconductor substrate, a conductive pad over said semiconductor substrate, and a separating layer over said semiconductor substrate,

forming a first conductive layer on a contact point of said conductive pad and over said separating layer;

forming a second conductive layer on said first conductive layer;

forming a first photoresist layer over said semiconductor substrate;

electroplating a conductive interconnect in a first opening in said first photoresist layer, in which the conductive interconnect is coupled to said contact point through said second conductive layer;

forming a nickel-containing layer over said conductive interconnect and in said first opening, in which the nickel-containing layer has a width greater than a width of said conductive interconnect;

forming a solder over said nickel-containing layer, in which the solder has a width equal to the width of said nickel-containing layer;

and removing said first conductive layer not under said second conductive layer, whereby said second conductive layer has a sidewall not covered by said first conductive layer, whereby an underfill is configured to be between said first device and a second device configured to be bonded with said first device and to contact said first and second devices and a sidewall of said conductive interconnect.

36. The method of claim 35, wherein said forming said first conductive layer comprises forming a titanium-containing layer.

37. The method of claim 35, wherein said forming said first conductive layer comprises forming a tantalum-containing layer.

38. The method of claim 35, after said electroplating said conductive interconnect, further comprising forming a nickel-containing layer over said conductive interconnect and in said second opening, followed by said removing said first photoresist layer.

39. The method of claim 35, after said electroplating said conductive interconnect, further comprising forming a gold-containing layer over said conductive interconnect and in said second opening, followed by said removing said first photoresist layer.

40. The method of claim 35, after said electroplating said conductive interconnect, further comprising forming a solder over said conductive interconnect and in said second opening, followed by said removing said first photoresist layer.

41. The method of claim 35, wherein said forming said second conductive layer comprises an electroplating process.

42. The method of claim 35, after said forming said first conductive layer, further comprising forming a second photoresist layer on said first conductive layer, wherein a second opening in said second photoresist layer exposes a region of said first conductive layer, next said forming said second conductive layer further on said region and in said second opening, and then removing said second photoresist layer.