Semiconductor device

• US 8,482,001 B2
• Filed: 12/22/2010
• Issued: 07/09/2013
• Est. Priority Date: 12/25/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): Tran, Tran
• Application Number:
  US12/976,582
• Publication Number:
  US 20110156117A1
• Time in Patent Office: 930 Days
• Field of Search: 257/43, 257/E29.296, 257/72, 257/83, 257/157, 257/290, 257/E27.112, 257/E27.131
• US Class Current: 257/43
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.

Claims

1. A semiconductor device comprising:

a transistor comprising;

a source electrode and a drain electrode;

an oxide semiconductor layer overlapping with the source electrode and the drain electrode; and

a gate insulating layer overlapping with the oxide semiconductor layer, and

a capacitor comprising the oxide semiconductor layer, one of the source electrode and the drain electrode, and an upper electrode, wherein the transistor has a top-gate structure, and

wherein the oxide semiconductor layer directly contacts with the source electrode and the drain electrode.

2. The semiconductor device according to claim 1, wherein the capacitor further comprises the gate insulating layer between the one of the source electrode and the upper electrode.

3. The semiconductor device according to claim 1, wherein edge portions of the source electrode and the drain electrode are tapered.

10. The semiconductor device according to claim 1, wherein the transistor further comprises an insulating layer over the one of the source electrode and the drain electrode.

13. The semiconductor device according to claim 1, wherein the transistor further comprises a gate electrode over the gate insulating layer.

15. The semiconductor device according to claim 1, wherein the source electrode and the drain electrode is located over a substrate.

4. A semiconductor device comprising:

a transistor comprising;

a source electrode and a drain electrode;

an oxide semiconductor layer overlapping with the source electrode and the drain electrode; and

a gate insulating layer overlapping with the oxide semiconductor layer, and

a capacitor comprising;

a pair of electrodes; and

the oxide semiconductor layer between the pair of electrodes,

wherein the transistor has a top-gate structure, and

wherein one of the source electrode and the drain electrode of the transistor and one of the pair of electrodes of the capacitor are directly connected to each other.

5. The semiconductor device according to claim 4, wherein the capacitor further comprises the gate insulating layer between the pair of electrodes.

6. The semiconductor device according to claim 4, wherein edge portions of the source electrode and the drain electrode are tapered.

11. The semiconductor device according to claim 4, wherein the transistor further comprises an insulating layer over the one of the source electrode and the drain electrode.

14. The semiconductor device according to claim 4, wherein the transistor further comprises a gate electrode over the gate insulating layer.

16. The semiconductor device according to claim 4 wherein the source electrode and the drain electrode is located over a substrate.

7. A semiconductor device comprising:

a transistor comprising;

a source electrode and a drain electrode;

an oxide semiconductor layer over the source electrode and the drain electrode;

a gate insulating layer over the oxide semiconductor layer; and

a gate electrode over the gate insulating layer, and

a capacitor comprising the oxide semiconductor layer,

wherein one of the source electrode and the drain electrode of the transistor and one electrode of the capacitor are directly connected to each other.

8. The semiconductor device according to claim 7, wherein the capacitor further comprises the gate insulating layer between the one of the source electrode and the drain electrode and the other electrode of the capacitor.

9. The semiconductor device according to claim 7, wherein edge portions of the source electrode and the drain electrode are tapered.

12. The semiconductor device according to claim 7, wherein the transistor further comprises an insulating layer over the one of the source electrode and the drain electrode.

17. The semiconductor device according to claim 7, wherein the source electrode and the drain electrode is located over a substrate.