Semiconductor device

• US 8,482,038 B2
• Filed: 07/10/2012
• Issued: 07/09/2013
• Est. Priority Date: 03/03/2006
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Sasaki, Takayuki, Igarashi, Yasuto, Morino, Naozumi
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): NGUYEN, CUONG B
• Application Number:
  US13/545,553
• Publication Number:
  US 20120280741A1
• Time in Patent Office: 364 Days
• Field of Search: None
• US Class Current: 257/210
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating

Abstract

A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.

Claims

1. A semiconductor device comprising:

a core area surrounded by a plurality of I/O areas;

a first one of said plurality of I/O areas configured to receive a first supply voltage;

a second one of said plurality of I/O areas configured to receive a second supply voltage which is lower than the first supply voltage;

a first I/O circuit included in the first one of said plurality of I/O areas;

a second I/O circuit included in the second one of said plurality of I/O areas;

first and second signal wires; and

first and second shield wires each running parallel to the first and the second signal wires,

wherein the first I/O circuit receives a first and a second signal outputted from the second I/O circuit via the first and the second signal wires, and outputs a level shifted signal from the second supply voltage to the first supply voltage,

wherein the second signal is inverted with respect to the first signal,

wherein the first and the second signal wires pass over a plurality of I/O cells included in the plurality of I/O areas, and

wherein a length of the first signal wire portion which passes over top surfaces of the plurality of I/O cells is equal to a length of the second signal wire portion which passes over the top surfaces of the plurality of I/O cells.

2. The semiconductor device according to claim 1, wherein each of the first shield wire and the second shield wire comprise a plurality of wires having a same electric potential.

3. The semiconductor device according to claim 1, wherein a power wire thicker than the first signal wire lies in a layer over the first signal wire and the second signal wire.

4. The semiconductor device according to claim 1, wherein a semiconductor substrate lies in a layer under the first and the second signal wires, and the first and second shield wires and the semiconductor substrate have a same electric potential.

5. The semiconductor device according to claim 1, wherein a buffer cannot be inserted midway between ends of each of the first and second signal wires.

6. The semiconductor device according to claim 1, wherein the length of each of the first and second signal wires is longer than a length of one edge of a semiconductor chip constituting the semiconductor device.

7. The semiconductor device according to claim 1, wherein the first signal wire and the first shield wire, and the second signal wire and the second shield wire, are multilayered.

8. The semiconductor device according to claim 1, wherein the first I/O circuit comprises a level up shift circuit.