Semiconductor device and the method of manufacturing the same

• US 8,482,061 B2
• Filed: 06/09/2011
• Issued: 07/09/2013
• Est. Priority Date: 06/10/2010
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Nishimura, Takeyoshi
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Karimy, Timor
• Application Number:
  US13/067,575
• Publication Number:
  US 20110303925A1
• Time in Patent Office: 761 Days
• Field of Search: 257/330, 257/77, 257/E29.262, 257/E21.334
• US Class Current: 257/330
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device according to the invention includes p-type well region 3 and n⁺ source region 4, both formed selectively in the surface portion of n⁻ drift region 2; trench 6 in contact with n⁺ source region 4 and extending through p-type well region 3 into n⁻ drift region 2; field plate 8 formed in trench 6 with first insulator film 7 interposed between the trench 6 inner surface and field plate 8; gate electrode 10 formed in trench 6 with second insulator film 9 interposed between the trench 6 side wall and gate electrode 10, gate electrode 10 being formed above field plate 8; first insulator film 7 being thicker than second insulator film 9; and n⁻⁻ lightly doped region 21 in n⁻ drift region 2, n⁻⁻ lightly doped region 21 crossing under the bottom surface of trench 6 from the corner portion thereof, n⁻⁻ lightly doped region 21 covering the bottom surface of trench 6.

The semiconductor device according to the invention and the method of manufacturing the semiconductor device according to the invention facilitate lowering the ON-state voltage, preventing the breakdown voltage from lowering, lowering the gate capacitance, and reducing the manufacturing costs.

Claims

1. A semiconductor device comprising;

a first semiconductor region of a first conductivity type;

a second semiconductor region of a second conductivity type disposed on the first semiconductor region;

a third semiconductor region of the first conductivity type disposed selectively on the second semiconductor region;

a trench extending through the third and second semiconductor regions and into the first semiconductor region;

a first electrode disposed in the trench with a first insulator film interposed between a side wall of the trench and the first electrode, the first electrode being located in a bottom portion of the trench;

a control electrode disposed in the trench with a second insulator film interposed between the side wall of the trench and the control electrode, the control electrode being located above the first electrode;

a second electrode in contact with the third semiconductor region; and

a fourth semiconductor region of the first conductivity type covering a corner portion of the trench, the fourth semiconductor region being doped more lightly than the first semiconductor region,

wherein the first electrode is positioned on a first semiconductor region side of a boundary between the first semiconductor region and the second semiconductor region,

wherein the first electrode is connected electrically to the second electrode, and

wherein the first insulator film is thicker than the second insulator film.

2. The semiconductor device according to claim 1, wherein the fourth semiconductor region crosses under the bottom of the trench from the corner portion of the trench such that the fourth semiconductor region covers the bottom of the trench.

3. The semiconductor device according to claim 1, wherein an impurity concentration in the fourth semiconductor region is 20% or more and 88% or less of an impurity concentration in the first semiconductor region.

4. The semiconductor device according to claim 1, wherein the semiconductor device is fabricating on a silicon substrate.

5. The semiconductor device according to claim 1, wherein the semiconductor device is fabricated on a silicon carbide substrate.