Post passivation interconnection schemes on top of IC chip
First Claim
Patent Images
1. A chip comprising:
- a silicon substrate;
a first internal circuit in or on said silicon substrate;
a second internal circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit;
a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit;
a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride, wherein one of multiple openings in said passivation layer has a diameter between 0.5 and 30 micrometers;
a first via in one of said multiple openings, wherein said first via is connected to said first interconnecting structure;
a second via in one of said multiple openings, wherein said second via is connected to said second interconnecting structure; and
a clock bus over said passivation layer, wherein said clock bus is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.
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Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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Citations
36 Claims
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1. A chip comprising:
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a silicon substrate; a first internal circuit in or on said silicon substrate; a second internal circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride, wherein one of multiple openings in said passivation layer has a diameter between 0.5 and 30 micrometers; a first via in one of said multiple openings, wherein said first via is connected to said first interconnecting structure; a second via in one of said multiple openings, wherein said second via is connected to said second interconnecting structure; and a clock bus over said passivation layer, wherein said clock bus is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A chip comprising:
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a silicon substrate; a first internal circuit in or on said silicon substrate; a second internal circuit in or on said silicon substrate; a dielectric system over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric system, wherein said first interconnecting structure is connected to said first internal circuit; a second interconnecting structure over said silicon substrate and in said dielectric system, wherein said second interconnecting structure is connected to said second internal circuit; multiple metal layers in said dielectric system, wherein said dielectric system comprises multiple dielectric layers between said multiple metal layers; a passivation layer over said dielectric system and over said multiple metal layers, wherein said passivation layer comprises a nitride; a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure; a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure; and a clock bus over said passivation layer, wherein said clock bus has a thickness greater than 1 micrometer, wherein said clock bus is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A chip comprising:
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a silicon substrate; a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises an electroplated damascene metal; a dielectric layer between said first and second metal layers; a passivation layer over said metallization structure and said dielectric layer, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 30 micrometers; and a metal interconnect connected to said first contact point through said first opening, wherein said metal interconnect comprises electroplated copper. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A chip comprising:
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a silicon substrate; a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises an electroplated damascene metal; a dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and said dielectric layer, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 30 micrometers; and a second metallization structure on said first contact point and over said passivation layer, wherein said second metallization structure is connected to said first contact point through said first opening, wherein said second metallization structure comprises electroplated copper. - View Dependent Claims (32, 33, 34, 35, 36)
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Specification