Universal digital block interconnection and channel routing

• US 8,482,313 B2
• Filed: 05/02/2011
• Issued: 07/09/2013
• Est. Priority Date: 04/17/2007
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren, Sullam, Bert, Mohammed, Haneef
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US13/099,334
• Publication Number:
  US 20110304354A1
• Time in Patent Office: 799 Days
• Field of Search: None
• US Class Current: 326/41
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4009 with data restructuring
• CPC Class Codes: H03K 19/177 arranged in matrix form

Abstract

A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.

Claims

1. An apparatus, comprising:

a plurality of digital blocks arranged into one or more pairs;

a programmable interconnect matrix including a first set of routing channels that programmably couple at least the two digital blocks of the one or more pairs together and segmentation elements that programmably interconnect two or more of the first set of routing channels together; and

a micro-controller system programmably coupled to the plurality of digital blocks and to one or more Inputs/Outputs (I/Os) through the programmable interconnect matrix.

2. The apparatus of claim 1, wherein at least one of the plurality of digital blocks is a programmable digital block.

3. The apparatus of claim 1, wherein the micro-controller system comprises:

a micro-controller coupled to the programmable interconnect matrix; and

a Direct Memory Access (DMA) controller coupled to the programmable interconnect matrix.

4. The apparatus of claim 3, wherein the micro-controller system, the plurality of digital blocks, the one or more I/Os, and the programmable interconnect matrix are all located in a same integrated circuit.

5. The apparatus of claim 1, wherein the micro-controller system comprises:

a micro-controller coupled to the programmable interconnect matrix; and

an interrupt controller coupled to the programmable interconnect matrix.

6. The apparatus of claim 5, wherein the micro-controller system, the plurality of digital blocks, the one or more I/Os, and the programmable interconnect matrix are all located in a same integrated circuit.

7. The apparatus of claim 1, further comprising a configuration memory coupled to the micro-controller system.

8. The apparatus of claim 1, further comprising a memory device accessible by the micro-controller system to control how the one or more of the plurality of digital blocks connect to the first set of routing channels.

9. The apparatus of claim 8, wherein the memory device is accessible by the micro-controller system to control how the first set of routing channels connect to the segmentation elements.

10. The apparatus of claim 1, wherein the segmentation elements comprises:

horizontal segmentation switches that programmably couple together the first set of routing channels in a same row; and

vertical segmentation switches that programmably couple together the first set of routing channels in one or more rows through a second set of routing channels.

11. The apparatus of claim 1, further comprising:

programmably selectable channel switches configured to connect one or more selectable signals from the plurality of digital bocks to associated ones of the first set of routing channels; and

programmable tri-state buffers in the segmentation elements configured to selectively couple together and drive signals between the associated ones of the first set of routing channels.

12. A method, comprising:

programming an interconnect matrix to connect two or more functional elements to a first set of routing channels, wherein the two or more functional elements are arranged into one or more pairs, the pairs being coupled together through one or more of the first set of routing channels;

programming the interconnect matrix to interconnect two or more of the first set of routing channels together;

writing, by a micro-controller system, a first set of values into a configuration memory that control connections between the two or more functional elements and the first set of routing channels.

13. The method of claim 12, further comprising:

writing, by the micro-controller system, a second set of values into the configuration memory that control the interconnections between the two or more of the first set of routing channels; and

writing, by the micro-controller system, a third set of values into the configuration memory that control the interconnections between the first set of routing channels and a second set of routing channels.

14. The method of claim 13, further comprising programming the interconnect matrix to further connect the two or more of the first set of routing channels to each other through the second set of routing channels.

15. The method of claim 12, wherein the one or more functional elements comprises one or more programmable digital blocks.

16. The method of claim 12, further comprising programming one or more paths through the interconnect matrix that connect one or more external pins or one or more internal functional elements to a same interrupt line on an internal interrupt controller.

17. The method of claim 12, further comprising programming one or more paths through the interconnect matrix that connect one or more external pins or one or more internal functional elements to a same Direct Memory Access (DMA) line on an internal DMA controller.

18. An apparatus, comprising:

a plurality of digital blocks arranged into one or more pairs;

a programmable interconnect matrix including a first set of routing channels that programmably couple at least the two digital blocks of the one or more pairs together and segmentation elements that programmably interconnect two or more of the first set of routing channels together; and

a micro-controller system programmably coupled to the plurality of digital blocks, to at least one Input/Output (I/O), and a fixed function peripheral through the programmable interconnect matrix.

19. The apparatus of claim 18, wherein the micro-controller system comprises:

a micro-controller coupled to the programmable interconnect matrix; and

a Direct Memory Access (DMA) controller coupled to the programmable interconnect matrix.

20. The apparatus of claim 19, wherein the micro-controller system, the plurality of digital blocks, the I/O port, and the programmable interconnect matrix are all located in a same integrated circuit.

21. The apparatus of claim 18, wherein the micro-controller system comprises:

a micro-controller coupled to the programmable interconnect matrix; and

an interrupt controller coupled to the programmable interconnect matrix.

22. The apparatus of claim 21, wherein the micro-controller system, the plurality of digital blocks, the I/O port, and the programmable interconnect matrix are all located in a same integrated circuit.