Dual pinned diode pixel with shutter

• US 8,482,642 B2
• Filed: 10/31/2011
• Issued: 07/09/2013
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Rysinski, Jeffrey
• Primary Examiner(s): OSINSKI, MICHAEL S
• Application Number:
  US13/285,599
• Publication Number:
  US 20120044396A1
• Time in Patent Office: 617 Days
• Field of Search: 348294-324, 250/208.1, 257291-292, 257/359, 257431-445
• US Class Current: 348/296
• CPC Class Codes: H04N 25/53 Control of the integration time
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion

Abstract

A pixel having an electronic shutter suitable for use in a pixel array of an imaging device includes a pinned diode and a shutter transistor. The pinned diode is utilized as a storage device while the shutter transistor controls charge transfer from the electronic shutter. The use of a pinned diode as a charge storage device for the electronic shutter permits greater charge transfer efficiency, has lower leakage (or “dark” current), and permits the resulting pixel to have a greater fill factor than pixels utilizing conventional electronic shutter circuits.

Claims

1. A circuit for storing and transferring charge from a light sensitive element of a pixel to a floating diffusion node, said circuit comprising:

a pinned diode charge storage element;

a shutter control element, said shutter control element having a shutter control input coupled to said light sensitive element and an output coupled to said pinned diode charge storage element; and

a transfer control element for transferring charge from said pinned diode charge storage element to said floating diffusion node.

2. The circuit of claim 1, wherein said pinned diode charge storage element comprises a pinned photodiode.

3. The circuit of claim 1, further comprising a light shielding element arranged to shield said pinned diode charge storage element from substantially all light incident upon said light sensitive element.

4. The circuit of claim 1, wherein said shutter control element is a transistor having one source/drain coupled to said pinned diode charge storage element and another source/drain coupled to said light sensitive element.

5. The circuit of claim 1, wherein said transfer control element is a transistor having one source/drain coupled to said pinned diode charge storage element and another source/drain coupled to said floating diffusion node.

6. A pixel comprising:

a light sensitive element for generating photo generated charge;

a shutter circuit for receiving charge from said light sensitive element, said shutter circuit comprising;

a pinned diode charge storage element; and

a shutter control element, said shutter control element having an input coupled to said light sensitive element and an output coupled to said pinned diode charge storage element; and

a transfer control element for transferring charge from said pinned diode charge storage element to a floating diffusion node.

7. The pixel of claim 6, wherein said pinned diode charge storage element comprises a pinned photodiode.

8. The pixel of claim 6, wherein said light sensitive element is a photodiode.

9. The pixel of claim 8, wherein said photodiode is a pinned photodiode.

10. The pixel of claim 6, wherein said shutter control element is a transistor having a gate configured to receive a global shutter control signal.

11. The pixel of claim 10, wherein said transfer control element is a second transistor having a gate configured to receive a row readout signal.

12. A method of operating an imager, the method comprising:

in each pixel of a plurality of pixels;

generating charge in a light sensitive element based on a received incident light;

selectively coupling said light sensitive element to a pinned diode charge storage element;

storing generated charges from said light sensitive element at said pinned diode charge storage element; and

selectively coupling said pinned diode charge storage element to a floating diffusion node.

13. The method of claim 12, further comprising:

storing charges from said pinned diode charge storage element at said floating diffusion node; and

selectively coupling said floating diffusion node to an output line using readout circuitry.

14. The method of claim 13, wherein selectively coupling said floating diffusion node to said output line using readout circuitry further comprises activating a row select transistor to transfer said charge from said floating diffusion node across an amplifier circuit onto said output line.

15. The method of claim 12, further comprising:

prior to selectively coupling said pinned diode charge storage element to said floating diffusion node, selectively coupling said floating diffusion node to a reset voltage.

16. The method of claim 12, further comprising:

after selectively coupling said pinned diode charge storage element to said floating diffusion node, selectively coupling said floating diffusion node to a reset voltage.

17. The method of claim 12, further comprising, prior to selectively electrically coupling said pinned diode charge storage element to said floating diffusion node, selectively de-coupling said pinned diode charge storage element to said light sensitive element.

18. The method of claim 12, wherein selectively electrically coupling said light sensitive element to said pinned diode charge storage element further comprises electrically coupling said respective light sensitive elements in each pixel of said plurality of pixels to respective pinned diode charge storage elements at a same time.

19. The method of claim 18, wherein said plurality of pixel comprises pixels arranged in rows and columns, and wherein selectively electrically coupling said pinned diode charge storage element to said floating diffusion node further comprises electrically coupling said respective pinned diode charge storage element in each pixel of said plurality of pixels to respective floating diffusion nodes on a row-by-row basis.