Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material

• US 8,482,973 B2
• Filed: 08/07/2012
• Issued: 07/09/2013
• Est. Priority Date: 12/19/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Herner, S. Brad, Bandyopadhyay, Abhijit
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US13/568,834
• Publication Number:
  US 20120300533A1
• Time in Patent Office: 336 Days
• Field of Search: 365/148, 365/174, 365/175
• US Class Current: 365/175
• CPC Class Codes: G11C 11/36 using diodes, e.g. as threshold elements , i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 27/1021 including diodes only

Abstract

A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. In addition, no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor. Numerous other aspects are provided.

Claims

1. A memory cell comprising:

a first conductor;

a second conductor;

a semiconductor junction diode between the first and second conductors,

wherein;

the semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode, and

no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor.

2. The memory cell of claim 1, wherein the semiconductor junction diode comprises silicon, germanium, or a silicon-germanium alloy.

3. The memory cell of claim 1, wherein the memory cell does not comprise a dielectric antifuse layer.

4. The memory cell of claim 1, wherein the memory cell does not comprise a chalcogenide material.

5. The memory cell of claim 1, wherein the semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 4 percent with the semiconductor junction diode.

6. The memory cell of claim 1, further comprising a layer of titanium nitride, tungsten nitride, tantalum nitride, tantalum, tungsten, or titanium tungsten in contact with the semiconductor junction diode.

7. The memory cell of claim 1, wherein the semiconductor junction diode is not in contact with titanium silicide, cobalt silicide, or nickel monosilicide.

8. The memory cell of claim 1, wherein, before programming, the semiconductor junction diode has a first maximum barrier height, and after programming, the semiconductor junction diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height.

9. A method comprising:

forming a semiconductor junction diode between first and second conductors;

crystallizing the semiconductor junction diode, wherein during the crystallizing step, the semiconductor junction diode is not in contact with a template material having a lattice mismatch of less than 12 percent with the semiconductor junction diode; and

programming the memory cell by applying a programming voltage between the first and second conductors,

wherein no resistance-switching element having its resistance changed by application of the programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor.

10. The method of claim 9, wherein the semiconductor junction diode comprises silicon, germanium, or a silicon-germanium alloy.

11. The method of claim 9, wherein the memory cell does not comprise a dielectric antifuse layer.

12. The method of claim 9, wherein the memory cell does not comprise a chalcogenide material.

13. The method of claim 9, wherein, during the crystallization step, the semiconductor junction diode is not in contact with a template material having a lattice mismatch of less than 4 percent with the semiconductor junction diode.

14. The method of claim 9, wherein, during the crystallizing step, the semiconductor junction diode is in contact with titanium nitride, tungsten nitride, tantalum nitride, tantalum, tungsten, or titanium tungsten.

15. The method of claim 9, wherein, during the crystallizing step, the semiconductor junction diode is not in contact with titanium silicide, cobalt silicide, or nickel monosilicide.

16. The method of claim 9, wherein, before the programming step, the semiconductor junction diode has a first maximum barrier height, and after the programming step, the semiconductor junction diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height.

17. A monolithic three dimensional memory array comprising:

(a) a first memory level above a substrate, the first memory level comprising;

i) a first plurality of substantially parallel conductors;

ii) a second plurality of substantially parallel conductors above the first plurality of substantially parallel conductors; and

iii) a first plurality of pillars comprising semiconductor junction diodes, each pillar disposed between one of the first plurality of substantially parallel conductors and the second plurality of substantially parallel conductors,

wherein;

each semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode, and

no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between any of the semiconductor junction diodes and the first plurality of substantially parallel conductors or the second plurality of substantially parallel conductors; and

(b) a second memory level monolithically formed above the first memory level.

18. The monolithic three dimensional memory array of claim 17, wherein the semiconductor junction diodes comprise silicon, germanium, or a silicon-germanium alloy.

19. The monolithic three dimensional memory array of claim 17, wherein the semiconductor junction diodes comprise vertically oriented p-i-n diodes.

20. The monolithic three dimensional memory array of claim 17, wherein the second memory level comprises a second plurality of pillars comprising semiconductor junction diodes.