Semiconductor memory device and method for driving the same
First Claim
1. A semiconductor device comprising:
- a first signal line;
a second signal line;
a memory cell; and
a circuit,wherein the memory cell comprises;
a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region including a first semiconductor;
a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region including a second semiconductor; and
a first capacitor,wherein the first semiconductor is different from the second semiconductor,wherein the second drain electrode, an electrode of the first capacitor, and the first gate electrode are electrically connected to one another,wherein the second gate electrode is electrically connected to the circuit through the second signal line,wherein the second source electrode is electrically connected to the first signal line,andwherein the circuit is configured to output a second potential higher than a first potential to the second signal line in a case where the first potential is input to the circuit.
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Accused Products
Abstract
A semiconductor device includes a first signal line, a second signal line, a memory cell, and a potential converter circuit. The memory cell includes a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region; and a capacitor. The first channel formation region and the second channel formation region include different semiconductor materials. The second drain electrode, one electrode of the capacitor, and the first gate electrode are electrically connected to one another. The second gate electrode is electrically connected to the potential converter circuit through the second signal line.
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Citations
27 Claims
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1. A semiconductor device comprising:
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a first signal line; a second signal line; a memory cell; and a circuit, wherein the memory cell comprises; a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region including a first semiconductor; a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region including a second semiconductor; and a first capacitor, wherein the first semiconductor is different from the second semiconductor, wherein the second drain electrode, an electrode of the first capacitor, and the first gate electrode are electrically connected to one another, wherein the second gate electrode is electrically connected to the circuit through the second signal line, wherein the second source electrode is electrically connected to the first signal line, and wherein the circuit is configured to output a second potential higher than a first potential to the second signal line in a case where the first potential is input to the circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 25)
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9. A semiconductor device comprising:
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a first signal line; a second signal line; a source line; a word line; a bit line; a memory cell; and a circuit, wherein the memory cell comprises; a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region including a first semiconductor; a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region including a second semiconductor; and a first capacitor, wherein the first semiconductor is different from the second semiconductor, wherein the second drain electrode, one electrode of the first capacitor, and the first gate electrode are electrically connected to one another, wherein the second gate electrode is electrically connected to the circuit through the second signal line, wherein the second source electrode is electrically connected to the first signal line, wherein the other electrode of the first capacitor is electrically connected to the word line, wherein the first source electrode is electrically connected to the source line, wherein the first drain electrode is electrically connected to the bit line, and wherein the circuit is configured to output a second potential higher than a first potential to the second signal line in a case where the first potential is input to the circuit. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 26)
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17. A semiconductor device comprising:
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a signal line; a memory cell; and a circuit, wherein the memory cell comprises; a first transistor; a second transistor comprising a channel formation region including an oxide semiconductor; and a first capacitor, wherein a first terminal of the second transistor, a terminal of the first capacitor, and a gate terminal of the first transistor are electrically connected to one another, and wherein a gate terminal of the second transistor is electrically connected to the signal line, and wherein the circuit comprises; a first wiring; a third transistor, wherein a first terminal of the third transistor is electrically connected to the first wiring; a second capacitor, wherein a first terminal of the second capacitor, a second terminal of the third transistor, and the signal line are electrically connected to one another; a fourth transistor, wherein a first terminal of the fourth transistor is electrically connected to a second terminal of the second capacitor; and a second wiring electrically connected to a second terminal of the fourth transistor, wherein a gate terminal of the fourth transistor is directly connected to the first wiring, wherein the first wiring is provided so as to be supplied with a power supply potential, and wherein the second wiring is provided so as to be supplied with a power supply potential. - View Dependent Claims (18, 19, 20, 21, 22)
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23. A method for driving a semiconductor device, comprising:
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selecting an on state or an off state of a second transistor to hold charge in a node where a gate electrode of a first transistor, one of a source electrode and a drain electrode of the second transistor, and an electrode of a first capacitor are electrically connected to one another, wherein in a case where a potential is supplied to the node, a potential supplied to a gate electrode of the second transistor is higher than a power supply potential, wherein the second transistor comprises a channel formation region including an oxide semiconductor, wherein a method for supplying the potential supplied to the gate electrode of the second transistor through a first line comprises; a first period where a potential, configured to make a fourth transistor an on state, is applied to a gate electrode of the fourth transistor; and a second period where a potential, configured to make the fourth transistor an off state, is applied to the gate electrode of the fourth transistor and a potential is applied to a second line electrically connected to one of a source electrode and a drain electrode of a third transistor so as to bootstrap a potential of the first line after the first period, wherein one of a source electrode and a drain electrode of the forth transistor and a first electrode of a second capacitor are electrically connected to the first line, wherein a second electrode of the second capacitor is electrically connected to the other of the source electrode and the drain electrode of the third transistor, and wherein the other of the source electrode and the drain electrode of the fourth transistor is directly connected to a gate electrode of the third transistor. - View Dependent Claims (24, 27)
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Specification