Apparatus, system, and method for managing data in a solid-state storage device

• US 8,482,993 B2
• Filed: 05/01/2012
• Issued: 07/09/2013
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: Unification Technologies LLC (Acacia Research Corporation)
• Original Assignee: Fusion-IO Incorporated (Western Digital Corporation)
• Inventors: Strasser, John, Thatcher, Jonathan, Fillingim, Jeremy, Flynn, David, Smith, Lance, Wood, Robert, Peterson, James
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US13/461,628
• Publication Number:
  US 20120215961A1
• Time in Patent Office: 434 Days
• Field of Search: 365/189.09, 365/189.011, 365/189.16, 365/185.24, 365/185.29, 711/161, 711/103, 711/162
• US Class Current: 365/189.09
• CPC Class Codes: G06F 1/183 Internal mounting support structures, e.g. for printed circuit boards, internal connecting means for buses G06F13/409
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
• CPC Class Codes: G06F 2211/002 Bus
• CPC Class Codes: G06F 2211/103 Hybrid, i.e. RAID systems with parity comprising a mix of RAID types
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/70 Details relating to dynamic memory management
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 : Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0604 : Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0608 : Saving storage space on storage systems
• CPC Class Codes: G06F 3/0613 : in relation to throughput
• CPC Class Codes: G06F 3/0619 : in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0643 : Management of files
• CPC Class Codes: G06F 3/065 : Replication mechanisms
• CPC Class Codes: G06F 3/0652 : Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0656 : Data buffering arrangements
• CPC Class Codes: G06F 3/0659 : Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 : Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 : Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/52 : Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/54 : Interprogram communication
• CPC Class Codes: H04L 67/02 : based on web technology, e.g. hypertext transfer protocol [HTTP]
• CPC Class Codes: H04L 67/1097 : for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H05K 7/1444 : Complex or three-dimensional-arrangements; Stepped or dual mother boards
• CPC Class Codes: H05K 7/1487 : Blade assemblies, e.g. blade cases or inner arrangements within a blade
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus, system, and method are disclosed for improving performance in a non-volatile solid-state storage device. Non-volatile solid-state storage media includes a plurality of storage cells. An input module receives source data for storage in the plurality of storage cells of the non-volatile solid-state storage media. Some or all of the bits of the source data are transformed to take into account a voltage level of an empty state of the plurality of storage cells. A write module writes the transformed source data to the plurality of storage cells of the non-volatile solid-state storage media.

Claims

1. A method for transforming data for a non-volatile solid-state storage device, the method comprising:

receiving source data for storage in a plurality of storage cells of non-volatile solid-state storage media, bits of the source data having a source bias different from a bias for the plurality of storage cells;

transforming the bits of the source data to reduce a number of storage cells to be changed during programming to represent the source data; and

writing the transformed source data to the plurality of storage cells of the non-volatile solid-state storage media.

2. The method of claim 1, further comprising:

reading the transformed source data from the plurality of storage cells of the non-volatile solid-state storage media; and

converting the bits of the transformed source data back to original bit values for the source data such that a bias of the bits returns to the source bias.

3. The method of claim 1, wherein the transforming comprises shifting the bits within the source data according to a reversible algorithm such that a start position for data and metadata within the source data changes between writing the transformed source data to the plurality of storage cells and writing subsequent transformed source data to the plurality of storage cells.

4. The method of claim 1, wherein the bias for the plurality of storage cells is selected from the group consisting of a bias toward ones, a bias toward zeroes, and a bias toward a balance of ones and zeroes.

5. The method of claim 1, wherein the bias for the plurality of storage cells comprises a bias toward a binary pattern.

6. The method of claim 5, further comprising selecting the binary pattern based on a state of one or more other storage cells physically adjacent to the plurality of storage cells.

7. The method of claim 6, wherein the binary pattern satisfies a predefined voltage differential threshold between the one or more other storage cells and the plurality of storage cells.

8. The method of claim 6, further comprising selecting the binary pattern to reduce inter-cell interference between the plurality of storage cells and the one or more other storage cells physically adjacent to the plurality of storage cells.

9. The method of claim 1, wherein transforming the bits of the source data comprises reducing transitions between different symbols in the source data, each symbol associated with a voltage level of a storage cell of the plurality of storage cells.

10. The method of claim 1, wherein transforming the bits of the source data comprises flipping binary values of the bits to reduce the number of storage cells to be changed during programming to represent the source data.

11. The method of claim 1, wherein transforming the bits comprises pseudo-randomizing the values of the bits of the source data to reduce the number of storage cells to be changed during programming to represent the source data.

12. The method of claim 1, wherein transforming the bits comprises padding the source data with padding data having binary values that to reduce the number of storage cells to be changed during programming to represent the source data.

13. The method of claim 12, wherein transforming the bits further comprises:

compressing the source data; and

selecting a size of the padding data based on an amount of space gained by the compression.

14. The method of claim 1, wherein transforming the bits of the source data to reduce the number of storage cells to be changed during programming further comprises reducing the number of storage cells to be changed from an empty state of the plurality of the storage cells.

15. An apparatus comprising:

a bit randomization module configured to deterministically pseudo-randomize bits of source data for storage in a plurality of storage cells of non-volatile solid-state storage media, wherein the bits are pseudo-randomized to reduce a number of storage cells to be programmed to represent the source data;

a write module configured to write the pseudo-randomized source data to the plurality of storage cells of the non-volatile solid-state storage media; and

an inverse bit randomization module configured to convert the pseudo-randomized source data back to original bit values for the source data in response to reading the pseudo-randomized source data from the plurality of storage cells.

16. The apparatus of claim 15, wherein the bit randomization module is configured to whiten pseudo-randomize the bits of the source data by transforming binary data values for the bits of the source data to shift a source bias of the source data to increase a number of the bits of the source data to correlate to an erase state of the plurality of storage cells.

17. The apparatus of claim 15, wherein the bit randomization module is configured to pseudo-randomize the bits of the source data by reversibly pseudo-randomizing values of the bits of the source data.

18. The apparatus of claim 17, wherein reversibly pseudo-randomizing values of the bits comprises one or more of encrypting values of the bits, scrambling values of the bits, deterministically rearranging values of the bits, XORing values of the bits with a pseudorandom binary sequence, or pseudo-randomizing values of the bits using a linear feedback shift register.

19. A system comprising:

a processor;

one or more communications buses in communication with the processor;

an input module configured to receive source data from the processor over the one or more communications buses for storage in a plurality of storage cells of non-volatile solid-state storage media;

a bit modification module configured to increase a number of binary ones of the source data to reduce wear on a plurality of storage cells; and

a write module configured to write the adjusted source data to the plurality of storage cells of the non-volatile solid-state storage media.

20. The system of claim 19, further comprising a non-volatile solid-state storage device comprising the plurality of storage cells, the non-volatile solid-state storage device in communication with the processor over the one or more communications buses, the plurality of storage cells configured to store binary one values in response to an erase operation for the plurality of storage cells.

21. A method for transforming data for a non-volatile solid-state storage device, the method comprising:

receiving source data for storage in a plurality of storage cells of the non-volatile solid-state storage media;

changing the bits of the source data to reduce a number of storage cells to be transitioned during programming to represent the source data; and

writing the changed source data to the plurality of storage cells of the non-volatile solid-state storage media.

22. The method of claim 21, further comprising:

reading the changed source data from the plurality of storage cells; and

reversing the read source data back to original bit values for the source data.

23. The method of claim 21, wherein writing the changed source data to the plurality of storage cells further comprises transitioning a first number of the storage cells from an empty state to a different voltage level, wherein the first number is less than a second number of the storage cells that would be transitioned in a corresponding operation to write the unchanged source data to the plurality of storage cells.

24. An apparatus comprising:

means for receiving source data for storage in a plurality of storage cells of non-volatile solid-state storage media, bits of the source data representing a first quantity of binary ones;

means for increasing the number of binary ones of the source data to increase the life of the plurality of storage cells; and

means for writing a representation of the source data to the plurality of storage cells of the non-volatile solid-state storage media.

25. The apparatus of claim 24, further comprising:

means for reading the representation of the source data from the plurality of storage cells; and

means for reversing the representation of the source data back to original bit values for the source data.