Embedded control system with floating-point conversion
First Claim
1. An embedded control system provided with a microcomputer having a memory for storing data in a floating-point format and a central processing unit for performing arithmetic operations on the data in the floating-point format, whereinthe central processing unit converts discrete data in the floating-point format into discrete data in a significand-reduced floating-point format in which low-order bits of the significand of the discrete data in the floating-point format are deleted before the discrete data in the significand-reduced floating-point format is stored in the memory, andthe central processing unit performs an interpolation search on the discrete data in the floating- point format after the discrete data in the significand-reduced floating-point format is temporarily converted into the discrete data in the floating-point format in another memory while maintaining the discrete data in the significand-reduced floating-point format in the memory, andwherein the discrete data in the floating-point format is 4-byte data including a 1-bit sign bit, an 8-bit exponent part, and the 23-bit significand, and the discrete data in the significand-reduced floating-point format is 2-byte data including the 1-bit sign bit, the 8-bit exponent part, and the 16-bit significand and is obtained by deleting 16 low-order bits of the significand of the data in the floating-point format.
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Abstract
An embedded control system capable of ensuring precision in arithmetic with data in the floating-point format and also avoiding a shortage of the storage area of a memory is provided.
According to an embedded control system in the present invention, when discrete data in the floating-point format is stored in a read-only memory, the discrete data in the floating-point format is converted into data in a significand-reduced floating-point format before being stored. Here, a significand-reduced floating-point number is a number obtained by deleting low-order bits of the significand of a floating-point number. Further, an interpolation search is performed using discrete data, the discrete data in the significand-reduced floating-point format stored in the read-only memory is brought back to the discrete data in the floating-point format before an interpolation search being performed.
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11 Claims
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1. An embedded control system provided with a microcomputer having a memory for storing data in a floating-point format and a central processing unit for performing arithmetic operations on the data in the floating-point format, wherein
the central processing unit converts discrete data in the floating-point format into discrete data in a significand-reduced floating-point format in which low-order bits of the significand of the discrete data in the floating-point format are deleted before the discrete data in the significand-reduced floating-point format is stored in the memory, and the central processing unit performs an interpolation search on the discrete data in the floating- point format after the discrete data in the significand-reduced floating-point format is temporarily converted into the discrete data in the floating-point format in another memory while maintaining the discrete data in the significand-reduced floating-point format in the memory, and wherein the discrete data in the floating-point format is 4-byte data including a 1-bit sign bit, an 8-bit exponent part, and the 23-bit significand, and the discrete data in the significand-reduced floating-point format is 2-byte data including the 1-bit sign bit, the 8-bit exponent part, and the 16-bit significand and is obtained by deleting 16 low-order bits of the significand of the data in the floating-point format.
Specification