MLC self-RAID flash data protection scheme

• US 8,484,534 B2
• Filed: 06/27/2012
• Issued: 07/09/2013
• Est. Priority Date: 03/17/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Olbrich, Aaron K., Prins, Doug
• Primary Examiner(s): Wilson, Yolanda L
• Application Number:
  US13/535,243
• Publication Number:
  US 20120272106A1
• Time in Patent Office: 377 Days
• Field of Search: 714/745, 714/763, 714/718, 365/185.29
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

In a multiple level cell flash memory data storage device, a flash memory array has a plurality of blocks, where each block is an erase unit and has a plurality of pages, and a respective block includes a plurality of groups of pages. Each group of pages in the respective block includes an assigned parity page, and each page of the respective block has a plurality of sectors, including an assigned parity sector. The storage device is operable to program and erase data on a page at a predetermined speed, and detect an error rate for each page of a block and identify a group of high error pages based on the error rates. Further, the storage device is configured to apply a speed slower than the predetermined speed in programming and erasing data on the identified high error pages.

Claims

1. A method of managing a multiple level cell flash memory that is organized logically into blocks each including a plurality of pages, each page including a plurality of sequentially numbered sectors, the method comprising:

programming and erasing data on a page at a predetermined speed;

detecting an error rate for each page of a block and identifying a group of high error pages based on the error rates; and

applying a speed slower than the predetermined speed in programming and erasing data on the identified high error pages.

2. The method of claim 1, further comprising:

(a) identifying a parity block;

(b) choosing a parity sector in each page of a respective block;

(c) assigning the pages of the respective block into a plurality of groups;

(d) for each page of the respective block, calculating a sector parity value for data stored in the sectors in the page and storing the sector parity value in the parity sector of the page;

(e) prior to completing data writing into all pages of a group in the respective block, calculating a subset group parity for a subset of pages in the group, the subset of pages comprising a plurality of pages in the group in the respective block; and

(f) storing the subset group parity in the parity block.

3. The method of claim 2, wherein the group in the respective block comprises a first group, and the method further comprises:

(g) repeating steps (e) to (f) for an additional subset of pages in a second group distinct from the first group.

4. The method as in claim 2, wherein the sectors of each page are each assigned a sector number, the method further comprising:

(h) selecting a column parity page and calculating, for each sector number, a column parity for all sectors assigned the sector number in the pages of the respective block.

5. The method as in claim 2, wherein each group consists of 8 pages.

6. The method as in claim 2, wherein each multiple level cell of a plurality of multiple level cells in the multiple level cell flash memory is shared by two pages of the same group.

7. The method as in claim 2, wherein the parity block resides outside the flash memory.

8. The method as in claim 2, wherein the parity block resides on a non-volatile memory.

9. The method as in claim 2, wherein the subset group parity, for the subset of pages in the respective group, is erased after data is completely written into the pages of the respective group.

10. The method as in claim 2, wherein the subset group parity, for the subset of pages in the respective group, is saved after data is completely written into the pages of the respective group.

11. The method as in claim 2, wherein the subset group parity, for the subset of pages in the respective group, is calculated from data in half of the pages of the respective group.

12. A flash memory data storage system operable in accordance with the method of claim 1.

13. The method of claim 1, further comprising:

(a) choosing a parity sector in each page of a respective block;

(b) assigning the pages of the respective block into a plurality of groups, each group in the respective block including an assigned parity page;

(c) for each page of the respective block, calculating a sector parity value for data stored in the sectors in the page and storing the sector parity value in the parity sector of the page;

(d) calculating a group parity value for data stored in the pages of the group; and

(e) storing the group parity value in the assigned parity page.

14. A multiple level cell flash memory data storage device, comprising:

a flash memory array having a plurality of blocks, each block in the plurality of blocks comprising an erase unit and having a plurality of pages, a respective block including a plurality of groups of pages, each group of pages in the respective block including an assigned parity page;

each page of the respective block having a plurality of sectors, including an assigned parity sector;

wherein the device is operable to;

program and erase data on a page at a predetermined speed;

detect an error rate for each page of a block and identify a group of high error pages based on the error rates; and

apply a speed slower than the predetermined speed in programming and erasing data on the identified high error pages.

15. The multiple level cell flash memory data storage device of claim 14,

wherein the device is further operable, for a respective page,

to store data in data sectors of the respective page;

to store, in the assigned parity sector of the respective page, a sector parity value of the data stored in the data sectors of the respective page; and

wherein the device is further operable, for a respective group of pages in the respective block,

to store data in data pages of the respective group of pages; and

to store, in a parity block, a subset group parity value calculated for a subset of pages in the respective group prior to completing data writing into all pages of the respective group.

16. The multiple level cell flash memory data storage device of claim 15, wherein the device is operable to calculate and store in the parity block subset group parity values for multiple subsets of pages, each subset of pages in a distinct respective group.

17. The multiple level cell flash memory data storage device of claim 15, wherein the sectors of each page are each assigned a sector number, and the device is operable, for the respective group of pages, to select a column parity page for the respective block and to calculate, for each sector number, a column parity for all sectors assigned the sector number in the pages of the respective block.

18. The multiple level cell flash memory data storage device of claim 15, wherein each group consists of 8 pages.

19. The multiple level cell flash memory data storage device of claim 15, wherein the parity block resides outside the flash memory.

20. The multiple level cell flash memory data storage device of claim 15, wherein the parity block resides on a non-volatile memory.

21. The multiple level cell flash memory data storage device of claim 15, wherein the subset group parity, for the subset of pages in the respective group, is erased after data is completely written into the pages of the respective group.

22. The multiple level cell flash memory data storage device of claim 15, wherein the subset group parity, for the subset of pages in the respective group, is saved after data is completely written into the pages of the respective group.

23. The multiple level cell flash memory data storage device of claim 15, wherein the subset group parity, for the subset of pages in the respective group, is calculated from data in half of the pages of the respective group.

24. The multiple level cell flash memory data storage device of claim 15, wherein each multiple level cell of a plurality of multiple level cells in the multiple level cell flash memory is shared by two pages of the same group.

25. The multiple level cell flash memory data storage device of claim 15, wherein each multiple level cell of a plurality of multiple level cells in the multiple level cell flash memory is shared by two pages assigned to different groups.

26. The multiple level cell flash memory data storage device of claim 25, wherein the groups are each assigned a group number and wherein the pages sharing the respective multiple level cell are assigned consecutive group numbers.

27. The multiple level cell flash memory data storage device of claim 26, wherein one or more of the groups are assigned half the number of pages as assigned to each of the remainder of the groups of the respective block.

28. The multiple level cell flash memory data storage device of claim 14,

wherein the device is further operable, for a respective page,

to store data in data sectors of the respective page;

to store, in the assigned parity sector of the respective page, a sector parity value of the data stored in the data sectors of the respective page; and

wherein the device is further operable, for a respective group of pages in the respective block,

to store data in data pages of the respective group of pages; and

to store, in the parity page of the respective group, a group parity value of the data stored in the data pages of the respective group.