Bonding process and bonded structures

• US 8,485,416 B2
• Filed: 01/05/2012
• Issued: 07/16/2013
• Est. Priority Date: 04/30/2009
• Status: Active Grant

• Current Assignee: Silex Microsystems AB (Sai Microelectronics, Inc.)
• Original Assignee: Silex Microsystems AB (Sai Microelectronics, Inc.)
• Inventors: Ebefors, Thorbjorn, Kalvesten, Edward, Svedin, Niklas, Eriksson, Anders
• Primary Examiner(s): Walker, Keith
• Assistant Examiner(s): SAAD, ERIN BARRY
• Application Number:
  US13/344,099
• Publication Number:
  US 20120097733A1
• Time in Patent Office: 558 Days
• Field of Search: 228/122.1, 228/123.1, 228/124.1, 228/124.5, 228/178, 228/179.1, 257/E21.48
• US Class Current: 228/122.1
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29035 covering only the peripheral area of the surface to be connected
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/9211 Parallel connecting processes
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described.

Claims

1. A bonding structure connecting portions of two semiconductor substrates, comprising:

a first semiconductor substrate with an upper surface with an area carrying a CMOS structure;

a second semiconductor substrate defining a cap encapsulating and covering the first semiconductor substrate, including the monolithically integrated component;

an eutectic bond, comprised of a eutectic composition, bonding the second semiconductor to the first semiconductor, the eutectic bond defining a hermetic seal (S) along an outer perimeter of a portion the second semiconductor substrate, the seal enclosing the monolithically integrated component;

a cavity defined by a depression in the cap on a lower side of the cap facing the upper surface of the first semiconductor, the cavity covering the area carrying the monolithically integrated component;

signal routing lines extending from the monolithically integrated component;

first metal posts located on a top surface of each routing line; and

corresponding second metal posts extending downward from the lower surface of the second semiconductor substrate, the first and second posting in vertical alignment,

the first and second posts forming thermo compression bonds bonding and electrically connecting the second semiconductor to the first semiconductor,

the thermo compression bonds located inside the outer perimeter of the portion the second semiconductor substrate sealed by the eutectic bond,

wherein the thermo compression bonds are harder than the eutectic bond.

2. The bonding structure according to claim 1, wherein,

the first and second metal posts of the thermo compression bond each comprise gold, and

the eutectic composition comprises gold-tin.

3. A bonding structure for connecting portions of two semiconductor substrates, comprising:

a first semiconductor substrate with an upper surface comprising i) an area carrying a monolithically integrated component, ii) a first eutectic bond ring surrounding an area including the monolithically integrated component and defining a first half of a hermetic seal, the first eutectic bond ring having a first height, and iii) a first metal post within the area surrounded by the first eutectic bond ring and electrically connected to the monolithically integrated component, the first metal post having a second height; and

a second semiconductor substrate defining a cap for encapsulating and covering the first semiconductor substrate including the monolithically integrated component,

the second semiconductor substrate having a lower surface comprising i) second eutectic bond ring of a shape corresponding to the first eutectic bond ring and defining a second half of the hermetic seal, the second eutectic bond ring having a third height, and ii) a second metal post corresponding to the first post, the second metal post having a fourth height,

wherein the first eutectic bond ring comprises a first material of an eutectic composition and the second eutectic bond right comprises a different, second material of the eutectic composition, a relative amount of the first and second materials being such as to form the eutectic composition when brought together and heated above a melting point of the eutectic composition,

wherein the lower surface of the second semiconductor substrate is positionable over the upper surface of the first semiconductor so that with application of pressure and heat, at a temperature above a melting point of the eutectic composition, the first and second materials bond the upper surface of the first semiconductor substrate to the lower surface of the second semiconductor substrate with an eutectic bond comprised of the first and second eutectic bond rings, the eutectic bond defining the hermetic seal (S), the seal enclosing the monolithically integrated component, the first and second metal posts forming a thermo compression bond that bonds and electrically connects the second semiconductor to the first semiconductor, the thermo compression bond being harder than the eutectic bond.

4. The bonding structure of claim 3, wherein,

at least one of the second and fourth heights is less than a corresponding one of the first and third heights.

5. The bonding structure of claim 3, wherein the eutectic composition is AuSn eutectic.

6. The bonding structure of claim 3, wherein,

the first and second metal posts each comprise gold,

the first material of the eutectic composition is silicon, and

the second material of the eutectic composition is gold.

7. The bonding structure of claim 3, wherein,

the first and second metal posts each comprise gold.

8. The bonding structure of claim 3, wherein,

the first material of the eutectic composition is silicon, and

the second material of the eutectic composition is gold.