Manufacturing method for metal gate

• US 8,486,790 B2
• Filed: 07/18/2011
• Issued: 07/16/2013
• Est. Priority Date: 07/18/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lai, Kuo-Chih, Li, Ching-I, Lin, Yu-Shu, Hung, Ya-Jyuan, Lu, Yen-Liang, Wang, Yu-Wen, Yu, Hsin-Chih, Huang, Po-Cheng
• Primary Examiner(s): CAMPBELL, SHAUN M
• Application Number:
  US13/184,572
• Publication Number:
  US 20130023098A1
• Time in Patent Office: 729 Days
• Field of Search: 438/287, 257/E21.453
• US Class Current: 438/287
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.

Claims

1. A manufacturing method for a metal gate comprising steps of:

providing a substrate having a dielectric layer and a polysilicon layer formed thereon;

forming a protecting layer on the polysilicon layer by a surface modification, wherein the surface modification comprises at least one of thermal treatment, plasma treatment, and solution treatment;

forming a patterned hard mask on the protecting layer;

performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate;

forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate;

removing the dummy gate to form a gate trench on the substrate; and

forming a metal gate having a second height substantially equal to the first height in the gate trench.

2. The manufacturing method for a metal gate according to claim 1, wherein the protecting layer comprises a diamond-like carbon (DLC) layer or a silicon carbide (SiC) layer.

3. The manufacturing method for a metal gate according to claim 1, wherein the patterned hard mask defines a position of the dummy gate.

4. The manufacturing method for a metal gate according to claim 1, wherein the patterned hard mask comprises silicon nitride (SiN).

5. The manufacturing method for a metal gate according to claim 1, further comprising sequentially forming lightly-doped drains (LDDs) in the substrate at two sides of the dummy gate, a spacer on sidewalls of the dummy gate, and a source/drain in the substrate at two sides of the spacer after the first etching process.

6. The manufacturing method for a metal gate according to claim 1, wherein the multilayered dielectric structure comprises at least a contact etch stop layer (CESL) and an inter-layer dielectric (ILD) layer.

7. The manufacturing method for a metal gate according to claim 1, further comprising:

performing a first planarization process to remove a portion of the multilayered dielectric structure to expose the patterned hard mask; and

performing a second planarization process to remove a portion of the multilayered dielectric structure and the patterned hard mask to expose the protecting layer.

8. The manufacturing method for a metal gate according to claim 1, wherein the step of removing the dummy gate further comprises:

performing a second etching process to remove the protecting layer; and

performing a third etching process to remove the polysilicon layer after the second etching process.

9. The manufacturing method for a metal gate according to claim 8, wherein the second etching process comprises a dry etching process.

10. The manufacturing method for a metal gate according to claim 8, wherein the second etching process and the third etching process are performed in-situ.

11. The manufacturing method for a metal gate according to claim 1, wherein the step of forming the metal gate further comprises:

forming a work function metal layer in the gate trench;

forming a filling metal layer on the work function metal layer; and

performing a third planarization process to remove a portion of the work function metal layer and the filling metal layer to form the metal gate.

12. The manufacturing method for a metal gate according to claim 11, wherein the dielectric layer comprises a high dielectric constant (high-k) gate dielectric layer, and the work function metal layer and the filling metal layer are formed on the high-K gate dielectric layer.

13. The manufacturing method for a metal gate according to claim 11, further comprising sequentially removing a portion of the dielectric layer to form an interfacial layer and forming a high-K dielectric layer on the interfacial layer before forming the work function metal layer.