Semiconductor memory device
First Claim
1. A semiconductor memory device comprising:
- a first wiring;
a second wiring;
a third wiring;
a fourth wiring;
a fifth wiring; and
a memory unit comprising a first memory cell and a second memory cell,wherein the first to fourth wirings are parallel to one another,wherein the first wiring and the fifth wiring intersect with each other,wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor,wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor,wherein a drain of the first transistor is connected to a gate of the second transistor, one electrode of the first capacitor, and a source of the third transistor,wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor,wherein a gate of the first transistor is connected to the first wiring,wherein the other electrode of the first capacitor is connected to the second wiring,wherein a gate of the third transistor is connected to the third wiring,wherein the other electrode of the second capacitor is connected to the fourth wiring,wherein a drain of the second transistor is connected to a source of the fourth transistor,wherein a conductivity type of the first transistor is the same as a conductivity type of the third transistor,wherein a conductivity type of the second transistor is the same as a conductivity type of the fourth transistor, andwherein the conductivity type of the first transistor is different from the conductivity type of the second transistor.
1 Assignment
0 Petitions
Accused Products
Abstract
In a matrix including a plurality of memory cells, each in which a drain of a writing transistor is connected to a gate of a reading transistor and the drain is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line, a source of the writing transistor and a source of the reading transistor is connected to a bit line, and a drain of the reading transistor is connected to a reading word line. A conductivity type of the writing transistor is different from a conductivity type of the reading transistor. In order to increase the integration degree, a bias line may be substituted with a reading word line in another row, or memory cells are connected in series so as to have a NAND structure, and a reading word line and a writing word line may be shared.
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Citations
20 Claims
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1. A semiconductor memory device comprising:
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a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; and a memory unit comprising a first memory cell and a second memory cell, wherein the first to fourth wirings are parallel to one another, wherein the first wiring and the fifth wiring intersect with each other, wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor, wherein a drain of the first transistor is connected to a gate of the second transistor, one electrode of the first capacitor, and a source of the third transistor, wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor, wherein a gate of the first transistor is connected to the first wiring, wherein the other electrode of the first capacitor is connected to the second wiring, wherein a gate of the third transistor is connected to the third wiring, wherein the other electrode of the second capacitor is connected to the fourth wiring, wherein a drain of the second transistor is connected to a source of the fourth transistor, wherein a conductivity type of the first transistor is the same as a conductivity type of the third transistor, wherein a conductivity type of the second transistor is the same as a conductivity type of the fourth transistor, and wherein the conductivity type of the first transistor is different from the conductivity type of the second transistor. - View Dependent Claims (2, 3, 4)
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5. A semiconductor memory device comprising:
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a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; and a memory unit comprising a first memory cell and a second memory cell, wherein the first to fourth wirings are parallel to one another, wherein the first wiring and the fifth wiring intersect with each other, wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor, wherein a source of the first transistor is connected to the fifth wiring, wherein a drain of the first transistor is connected to a gate of the second transistor, one electrode of the first capacitor, and a source of the third transistor, wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor, wherein a gate of the first transistor is connected to the first wiring, wherein the other electrode of the first capacitor is connected to the second wiring, wherein a gate of the third transistor is connected to the third wiring, wherein the other electrode of the second capacitor is connected to the fourth wiring, wherein a source of the second transistor is connected to the fifth wiring, wherein a drain of the second transistor is connected to a source of the fourth transistor, wherein a conductivity type of the first transistor is the same as a conductivity type of the third transistor, wherein a conductivity type of the second transistor is the same as a conductivity type of the fourth transistor, and wherein the conductivity type of the first transistor is different from the conductivity type of the second transistor. - View Dependent Claims (6, 7, 8)
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9. A semiconductor memory device comprising:
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a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; and a memory unit comprising a first memory cell and a second memory cell, wherein the first to fourth wirings are parallel to one another, wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor, wherein a drain of the first transistor is connected to a gate of the second transistor, one electrode of the first capacitor, and a source of the third transistor, wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor, wherein a gate of the first transistor is connected to the first wiring, wherein the other electrode of the first capacitor is connected to the second wiring, wherein a gate of the third transistor is connected to the third wiring, wherein the other electrode of the second capacitor is connected to the fourth wiring, wherein a drain of the second transistor is connected to a source of the fourth transistor, wherein a drain of the fourth transistor is connected to the fifth wiring, wherein a conductivity type of the first transistor is the same as a conductivity type of the third transistor, wherein a conductivity type of the second transistor is the same as a conductivity type of the fourth transistor, and wherein the conductivity type of the first transistor is different from the conductivity type of the second transistor. - View Dependent Claims (10, 11, 12)
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13. A semiconductor memory device comprising:
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a substrate; a first conductive region over the substrate; a second conductive region over the substrate; a third conductive region over the substrate; a first gate over the substrate; a second gate over the substrate; a first wiring; a second wiring; a third wiring; a fourth wiring; and a fifth wiring, wherein the first to fourth wirings are parallel to one another, wherein the first wiring and the fifth wiring intersect with each other, wherein the first conductive region and the second conductive region are separated by the first gate, wherein the second conductive region and the third conductive region are separated by the second gate, wherein the second wiring is between the first wiring and the third wiring, wherein the third wiring is between the second wiring and the fourth wiring, wherein the second wiring overlaps with the first gate, wherein the fourth wiring overlaps with the second gate, and wherein each of the first to sixth conductive regions comprises a p-type semiconductor region. - View Dependent Claims (14, 15, 16)
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17. A semiconductor memory device comprising:
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a substrate; a first conductive region over the substrate; a second conductive region over the substrate; a third conductive region over the substrate; a first gate over the substrate; a second gate over the substrate; a first wiring; a second wiring; a third wiring; a fourth wiring; and wherein the first to fourth wirings are parallel to one another, wherein the first conductive region and the second conductive region are separated by the first gate, wherein the second conductive region and the third conductive region are separated by the second gate, wherein the second wiring is between the first wiring and the third wiring, wherein the third wiring is between the second wiring and the fourth wiring, wherein the second wiring overlaps with the first gate, wherein the fourth wiring overlaps with the second gate, and wherein each of the first to sixth conductive regions comprises a p-type semiconductor region. - View Dependent Claims (18, 19, 20)
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Specification