Semiconductor memory device

• US 8,487,303 B2
• Filed: 03/14/2011
• Issued: 07/16/2013
• Est. Priority Date: 03/19/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Primary Examiner(s): Pham, Long
• Application Number:
  US13/047,188
• Publication Number:
  US 20110228584A1
• Time in Patent Office: 855 Days
• Field of Search: 257/43, 257/57, 257/68, 257/71, 257/296, 257/369
• US Class Current: 257/43
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

In a matrix including a plurality of memory cells, each in which a drain of a writing transistor is connected to a gate of a reading transistor and the drain is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line, a source of the writing transistor and a source of the reading transistor is connected to a bit line, and a drain of the reading transistor is connected to a reading word line. A conductivity type of the writing transistor is different from a conductivity type of the reading transistor. In order to increase the integration degree, a bias line may be substituted with a reading word line in another row, or memory cells are connected in series so as to have a NAND structure, and a reading word line and a writing word line may be shared.

Claims

1. A semiconductor memory device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring;

a fifth wiring; and

a memory unit comprising a first memory cell and a second memory cell,

wherein the first to fourth wirings are parallel to one another,

wherein the first wiring and the fifth wiring intersect with each other,

wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor,

wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor,

wherein a drain of the first transistor is connected to a gate of the second transistor, one electrode of the first capacitor, and a source of the third transistor,

wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor,

wherein a gate of the first transistor is connected to the first wiring,

wherein the other electrode of the first capacitor is connected to the second wiring,

wherein a gate of the third transistor is connected to the third wiring,

wherein the other electrode of the second capacitor is connected to the fourth wiring,

wherein a drain of the second transistor is connected to a source of the fourth transistor,

wherein a conductivity type of the first transistor is the same as a conductivity type of the third transistor,

wherein a conductivity type of the second transistor is the same as a conductivity type of the fourth transistor, and

wherein the conductivity type of the first transistor is different from the conductivity type of the second transistor.

2. The semiconductor memory device according to claim 1, wherein the conductivity type of the second transistor is p-type.

3. The semiconductor memory device according to claim 1, wherein each of the first transistor and the third transistor comprises an oxide semiconductor.

4. The semiconductor memory device according to claim 1, wherein each of the second transistor and the fourth transistor comprises a single crystal silicon semiconductor.

5. A semiconductor memory device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring;

a fifth wiring; and

a memory unit comprising a first memory cell and a second memory cell,

wherein the first to fourth wirings are parallel to one another,

wherein the first wiring and the fifth wiring intersect with each other,

wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor,

wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor,

wherein a source of the first transistor is connected to the fifth wiring,

wherein a drain of the first transistor is connected to a gate of the second transistor, one electrode of the first capacitor, and a source of the third transistor,

wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor,

wherein a gate of the first transistor is connected to the first wiring,

wherein the other electrode of the first capacitor is connected to the second wiring,

wherein a gate of the third transistor is connected to the third wiring,

wherein the other electrode of the second capacitor is connected to the fourth wiring,

wherein a source of the second transistor is connected to the fifth wiring,

wherein a drain of the second transistor is connected to a source of the fourth transistor,

wherein a conductivity type of the first transistor is the same as a conductivity type of the third transistor,

wherein a conductivity type of the second transistor is the same as a conductivity type of the fourth transistor, and

wherein the conductivity type of the first transistor is different from the conductivity type of the second transistor.

6. The semiconductor memory device according to claim 5, wherein the conductivity type of the second transistor is p-type.

7. The semiconductor memory device according to claim 5, wherein each of the first transistor and the third transistor comprises an oxide semiconductor.

8. The semiconductor memory device according to claim 5, wherein each of the second transistor and the fourth transistor comprises a single crystal silicon semiconductor.

9. A semiconductor memory device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring;

a fifth wiring; and

a memory unit comprising a first memory cell and a second memory cell,

wherein the first to fourth wirings are parallel to one another,

wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor,

wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor,

wherein a drain of the first transistor is connected to a gate of the second transistor, one electrode of the first capacitor, and a source of the third transistor,

wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor,

wherein a gate of the first transistor is connected to the first wiring,

wherein the other electrode of the first capacitor is connected to the second wiring,

wherein a gate of the third transistor is connected to the third wiring,

wherein the other electrode of the second capacitor is connected to the fourth wiring,

wherein a drain of the second transistor is connected to a source of the fourth transistor,

wherein a drain of the fourth transistor is connected to the fifth wiring,

wherein a conductivity type of the first transistor is the same as a conductivity type of the third transistor,

wherein a conductivity type of the second transistor is the same as a conductivity type of the fourth transistor, and

wherein the conductivity type of the first transistor is different from the conductivity type of the second transistor.

10. The semiconductor memory device according to claim 9, wherein the conductivity type of the second transistor is p-type.

11. The semiconductor memory device according to claim 9, wherein each of the first transistor and the third transistor comprises an oxide semiconductor.

12. The semiconductor memory device according to claim 9, wherein each of the second transistor and the fourth transistor comprises a single crystal silicon semiconductor.

13. A semiconductor memory device comprising:

a substrate;

a first conductive region over the substrate;

a second conductive region over the substrate;

a third conductive region over the substrate;

a first gate over the substrate;

a second gate over the substrate;

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a fifth wiring,

wherein the first to fourth wirings are parallel to one another,

wherein the first wiring and the fifth wiring intersect with each other,

wherein the first conductive region and the second conductive region are separated by the first gate,

wherein the second conductive region and the third conductive region are separated by the second gate,

wherein the second wiring is between the first wiring and the third wiring,

wherein the third wiring is between the second wiring and the fourth wiring,

wherein the second wiring overlaps with the first gate,

wherein the fourth wiring overlaps with the second gate, and

wherein each of the first to sixth conductive regions comprises a p-type semiconductor region.

14. The semiconductor memory device according to claim 13, wherein an oxide semiconductor layer is between the first gate and the second wiring and between the second gate and the fourth wiring.

15. The semiconductor memory device according to claim 13, wherein the substrate is a single crystal silicon substrate.

16. The semiconductor memory device according to claim 13, wherein the fifth wiring is over the first to fourth wirings.

17. A semiconductor memory device comprising:

a substrate;

a first conductive region over the substrate;

a second conductive region over the substrate;

a third conductive region over the substrate;

a first gate over the substrate;

a second gate over the substrate;

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

wherein the first to fourth wirings are parallel to one another,

wherein the first conductive region and the second conductive region are separated by the first gate,

wherein the second conductive region and the third conductive region are separated by the second gate,

wherein the second wiring is between the first wiring and the third wiring,

wherein the third wiring is between the second wiring and the fourth wiring,

wherein the second wiring overlaps with the first gate,

wherein the fourth wiring overlaps with the second gate, and

wherein each of the first to sixth conductive regions comprises a p-type semiconductor region.

18. The semiconductor memory device according to claim 17, wherein an oxide semiconductor layer is between the first gate and the second wiring and between the second gate and the fourth wiring.

19. The semiconductor memory device according to claim 18, wherein the oxide semiconductor layer comprises a doped region.

20. The semiconductor memory device according to claim 17, wherein the substrate is a single crystal silicon substrate.