Low voltage power MOSFET device and process for its manufacture

• US 8,487,368 B2
• Filed: 04/27/2007
• Issued: 07/16/2013
• Est. Priority Date: 04/04/2000
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Thaper, Narash
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US11/796,303
• Publication Number:
  US 20070202650A1
• Time in Patent Office: 2,272 Days
• Field of Search: 438/270, 438/296, 438/589, 438/FOR.192, 257/E21.41, 257/E29.262, 257/E21.625, 257/330, 257/333
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low R_DSON and increased V_DSMAX and V_GSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000Å to 1400Å and the nitride is subsequently removed and a thin oxide, for example 320Å is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon. A very lightly doped diffusion of 1000Å to 2000Å in depth could also be formed around the bottom of the trench and is depleted at all times by the inherent junction voltage to further reduce Miller capacitance and switching loss.

Claims

1. A method for manufacturing a semiconductor device, said method comprising:

providing a semiconductor substrate;

epitaxially forming a semiconductor layer of first conductivity on said substrate;

forming a channel region with depth in said epitaxially formed semiconductor layer through implantation of dopants of second conductivity type, wherein said implantation introduces defects in said epitaxially formed semiconductor layer and wherein said implantation introduces surface damage with depth to said epitaxially formed semiconductor layer;

forming trenches, each trench with a bottom and a plurality of substantially vertical sidewalls in said epitaxially formed layer, said trenches extending through said channel region; and

forming at least one source region with depth in said channel region, wherein said at least one source region is adjacent to said trenches, and wherein said-depth of said at least one source region is greater than said depth of said surface damage.

2. A method according to claim 1, further comprising forming an oxide layer on said sidewalls of said trenches and a thick oxide layer on said bottom of said trenches, wherein said thick oxide layer at the bottom of said trenches is thicker than said oxide at said sidewalls of said trenches.

3. A method according to claim 2, wherein said thick oxide layer at the bottom of said trenches is formed by first covering said sidewall of said trenches with an oxidation retardant and then oxidizing said bottom of said trenches to a desired thickness.

4. A method according to claim 3, wherein said oxidation retardant is a nitride.

5. A method according to claim 2, wherein said thick oxide layer at the bottom of said trenches is formed by amorphizing the semiconductor material at said bottom of said trenches and then oxidizing said bottom of said trenches and said sidewalls of said trenches at the same time.

6. A method according to claim 2, wherein said thick oxide at said bottom of said trenches is between approximately 1000-1400 angstroms.

7. A method according to claim 2, wherein said oxide at said sidewalls of said trenches is between approximately 300-320 angstroms.

8. The method of claim 1, wherein the depth of said at least one source region is less than said depth of said channel region.

9. A low-power MOSEET device comprising:

a semiconductor substrate;

an epitaxially formed semiconductor layer of first conductivity formed over said semiconductor substrate;

a channel region with depth formed inside said epitaxially formed semiconductor layer,

wherein said channel region is formed through implantation of dopants of second conductivity type,

wherein said implantation of dopants introduces defects in said epitaxially formed semiconductor layer,

wherein said implantation introduces surface damage with depth to said epitaxially formed semiconductor layer, and

at least one trench, said trench comprising a bottom and a plurality of substantially vertical sidewalls, wherein said trench is formed in said epitaxially formed layer, and

wherein said trench extends through said channel region; and

at least one source region with depth, wherein said at least one source region resides inside said channel region,

wherein said at least one source region is adjacent to said trenches, and

wherein said depth of said at least one source region is greater than said depth of said surface damage.

10. The low-power MOSFET device of claim 9, wherein:

an oxide layer is formed on said sidewalls of said trench;

a thick oxide layer is formed on said bottom of said trench; and

said thick oxide layer at said bottom of said trench is thicker than said oxide layer at said sidewalls of said trench.

11. The low-power MOSFET device of claim 10, wherein said thick oxide layer at said bottom of said trench is formed by:

covering said sidewall of said trench with an oxidation retardant; and

subsequently oxidizing said bottom of said trenches to a desired thickness.

12. The low-power MOSFET device of claim 11, wherein said oxidation retardant is a nitride.

13. The low-power MOSFET device of claim 10, wherein said thick oxide layer at said bottom of said trenches is formed by:

amorphizing said semiconductor material at said bottom of said trenches; and

concurrently oxidizing said bottom of said trenches and said sidewalls of said trenches.

14. The low-power MOSFET device of claim 10, wherein said thick oxide at said bottom of said trench is between approximately 1000-1400 Angstroms.

15. The low-power MOSFET device of claim 10, wherein said oxide at said sidewalls of said trenches is between approximately 300-320 Angstroms.

16. The low-power MOSFET device of claim 10, wherein said depth of said at least one source region is less than said depth of said channel region.