Device scheme of HKMG gate-last process

• US 8,487,382 B2
• Filed: 11/09/2011
• Issued: 07/16/2013
• Est. Priority Date: 08/27/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chung, Sheng-Chen, Thei, Kong-Beng, Chuang, Harry
• Primary Examiner(s): AU, BAC H
• Application Number:
  US13/292,665
• Publication Number:
  US 20120056269A1
• Time in Patent Office: 615 Days
• Field of Search: 257/369, 257/407, 257/412, 257/E27.064, 257/E29.16
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.

Claims

1. An integrated circuit having metal gate stacks, comprising:

a semiconductor substrate;

a first gate stack of an n-type field-effect transistor, the first gate stack including;

a high k dielectric layer on the semiconductor substrate;

a titanium nitride layer on the high k dielectric material layer;

a first metal layer on the titanium nitride layer, the first metal layer comprised of one of titanium nitride and tantalum nitride; and

a second metal layer on the first metal layer such that the second metal layer physically contacts the first metal layer; and

a second gate stack of a p-type FET, the second gate stack including;

the high k dielectric layer on the semiconductor substrate;

the titanium nitride layer on the high k dielectric material layer;

a third metal layer on the titanium nitride layer, wherein the third metal layer is different from the first and second metal layers; and

a fourth metal layer on the third metal layer,

wherein the second metal layer comprises at least one of titanium aluminum and titanium aluminum nitride in physical contact with the first metal layer.

2. The integrated circuit of claim 1, wherein the second gate stack further comprises the first metal layer interposed the third metal layer and the titanium nitride layer.

3. The integrated circuit of claim 2, wherein the second metal layer and the fourth metal layer are substantially same in composition.

4. The integrated circuit of claim 1, wherein the first metal layer comprises tantalum nitride.

5. The integrated circuit of claim 1, wherein the third metal layer comprises one of titanium nitride and tungsten nitride.

6. An integrated circuit comprising:

a semiconductor substrate;

a first gate stack of an n-type field-effect transistor, the first gate stack including;

a high k dielectric layer on the semiconductor substrate;

a first metal layer disposed over the high k dielectric material layer;

a second metal layer on the first metal layer, the second metal layer being different than the first metal layer; and

a third metal layer on the second metal layer, the third metal layer being different than the second metal layer; and

a second gate stack of a p-type FET, the second gate stack including;

the high k dielectric layer on the semiconductor substrate;

the first metal layer disposed over the high k dielectric material layer;

a fourth metal layer on the first metal layer, the fourth metal layer being different than the first metal layer; and

a fifth metal layer on the fourth metal layer, the fifth metal layer being different than the fourth metal layer,

wherein one of the second, third, fourth, and fifth metal layers is a titanium aluminum layer.

7. The integrated circuit of claim 6, wherein the first metal layer comprises titanium nitride.

8. The integrated circuit of claim 6, wherein the third metal layer is formed of a first material and the fifth metal layer is formed of a second material, the first material being different from the second material.

9. The integrated circuit of claim 6, wherein the second metal layer and the fourth metal layer are substantially same in composition.

10. The integrated circuit of claim 6, wherein the first metal layer comprises titanium nitride,

wherein the second and fourth metal layers comprise tantalum nitride,

wherein the third metal layer is the titanium aluminum layer, and

wherein the fifth metal layer comprises one of tungsten nitride and titanium nitride.

11. The integrated circuit of claim 6, further comprising:

a sixth metal layer disposed over the fifth metal layer, the sixth metal layer and the third metal layer are substantially same in composition.

12. The integrated circuit of claim 11, further comprising:

a seventh metal layer interposed between the sixth metal layer and the fifth metal layer, the seventh metal layer including tungsten nitride.

13. The integrated circuit of claim 6, wherein the first metal layer comprises titanium nitride,

wherein the second metal layer is the titanium aluminum layer,

wherein the fourth metal layer comprises tungsten nitride, and

wherein the third metal layer and the fifth metal layer have different compositions.

14. An integrated circuit comprising:

a semiconductor substrate;

a first gate stack of an n-type field-effect transistor, the first gate stack including;

a high k dielectric layer on the semiconductor substrate;

a titanium nitride layer disposed on the high k dielectric material layer;

a first metal layer on the titanium nitride layer, the first metal layer being different than the titanium nitride layer;

a second metal layer on the first metal layer, the second metal layer being different than the first metal layer; and

wherein at least one of the first and second metal layers is a titanium aluminum layer, and

a second gate stack of a p-type FET, the second gate stack including;

the high k dielectric layer on the semiconductor substrate;

the titanium nitride layer on the high k dielectric material layer;

a third metal layer disposed over the titanium nitride layer; and

a fourth metal layer on the third metal layer, the fourth metal layer being different than the third metal layer.

15. The integrated circuit of claim 14, wherein the first metal layer is formed of a first material and the third metal layer is formed of a second material, the first material being different from the second material.

16. The integrated circuit of claim 14, wherein the first metal layer and the third metal layer are substantially same in composition.

17. The integrated circuit of claim 14, wherein the first metal layer is the titanium aluminum layer,

wherein the second metal layer comprises titanium nitride, and

wherein fourth metal layer is different than the second metal layer.

18. The integrated circuit of claim 14, wherein the first metal layer comprises tantalum nitride,

wherein the second metal layer is the titanium aluminum layer,

wherein the third metal layer comprises one of tantalum nitride and titanium nitride, and

wherein the fourth metal layer comprises one of titanium nitride, tungsten nitride, tungsten, and aluminum.

19. The integrated circuit of claim 14, further comprising:

a fifth metal layer disposed on the second metal layer, the fifth metal layer being different than the second metal layer, and

a sixth metal layer disposed on the fourth metal layer, the sixth metal layer being different than the fourth metal layer.

20. The integrated circuit of claim 14, wherein the second metal layer comprises only titanium aluminum.