High performance system-on-chip using post passivation process

• US 8,487,400 B2
• Filed: 10/23/2007
• Issued: 07/16/2013
• Est. Priority Date: 12/21/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US11/877,649
• Publication Number:
  US 20080042239A1
• Time in Patent Office: 2,093 Days
• Field of Search: 257/503, 257/508, 257/635, 257/684, 257/690, 257/296, 257/299, 257/303, 257/599, 257/602
• US Class Current: 257/508
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/642 : Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/647 : Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01084 : Polonium [Po]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 257/92 : Conductor layers on different levels connected in parallel, e.g. to reduce resistance

Abstract

The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Claims

1. An integrated circuit chip comprising:

a silicon substrate;

multiple semiconductor devices in or on said silicon substrate, wherein said multiple semiconductor devices comprise a transistor;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a contact point of said metallization structure, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride layer;

a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point, and wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer; and

a capacitor on said polymer layer, wherein said capacitor comprises a lower conductive plate on said polymer layer, a third dielectric layer on said lower conductive plate, and an upper conductive plate on said third dielectric layer, wherein said lower plate is connected to said contact point through said second opening, wherein said lower conductive plate has a thickness between 0.5 and 20 micrometers, wherein said upper conductive plate has a thickness between 0.5 20 micrometers.

2. The integrated circuit chip of claim 1, wherein said third dielectric layer comprises TiO₂.

3. The integrated circuit chip of claim 1, wherein said third dielectric layer comprises Ta₂O₅.

4. The integrated circuit chip of claim 1, wherein said polymer layer comprises polyimide.

5. The integrated circuit chip of claim 1, wherein said polymer layer comprises benzocyclobutene (BCB).

6. The integrated circuit chip of claim 1, wherein said passivation layer further comprises an oxide layer under said nitride layer.

7. The integrated circuit chip of claim 1, wherein said third dielectric layer has a thickness between 500 and 10,000 Angstroms.

8. An integrated circuit chip comprising:

a silicon substrate;

multiple semiconductor devices in or on said silicon substrate, wherein said multiple semiconductor devices comprise a transistor;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a contact point of said metallization structure, and said contact point is at a botom of said first opening, wherein said passivation layer comprises a nitride layer;

a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point, wherein said polymer layer has a thickness between 2 and 150 micrometers; and

a resistor on said polymer layer, wherein said resistor connects to said contact point through said second opening.

9. The integrated circuit chip of claim 8, wherein said resistor comprises tantalum.

10. The integrated circuit chip of claim 8, wherein said resistor comprises aluminum.

11. The integrated circuit chip of claim 8, wherein said resistor comprises molybdenum.

12. The integrated circuit chip of claim 8, wherein said polymer layer comprises polyimide.

13. The integrated circuit chip of claim 8, wherein said polymer layer comprises benzocyclobutene (BCB).

14. The integrated circuit chip of claim 8, wherein said passivation layer further comprises an oxide layer under said nitride layer.

15. An integrated circuit chip comprising:

a silicon substrate;

multiple semiconductor devices in or on said silicon substrate, wherein said multiple semiconductor devices comprises a transistor;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of a said first opening, and wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening;

a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers, wherein a third opening in said first polymer layer is over said first contact point, and a fourth opening in said first polymer layer is over said second contact point;

a coil on said first polymer layer, wherein said coil is connects to said first contact point through said third opening, wherein said coil comprises electroplated copper;

a metal line on said first polymer layer, wherein said metal line is connected to said second contact point through and fourth opening; and

a second polymer layer over said metal line.

16. The integrated circuit chip of claim 15, wherein said first polymer layer comprises polyimide.

17. The integrated circuit chip of claim 15, wherein said passivation layer further comprises an oxide layer under said nitride layer.

18. The integrated circuit chip of claim 15, wherein said second opening has a width between 0.5 and 30 micrometers.

19. The integrated circuit chip of claim 15, wherein said first opening has a width between 0.5 and 30 micrometers.

20. The integrated circuit chip of claim 15, wherein said metal line comprises a ground connection.

36. The integrated circuit chip of claim 15, wherein said passivation layer has a thickness less than said thickness of said first polymer layer.

37. The integrated circuit chip of claim 15, wherein a fifth opening in said passivation layer is over a third contact point of said metallization structure, and said third contact point is at a bottom of said fifth opening, wherein a sixth opening in said first polymer layer is over said third contact point, wherein said coil is connected to said third contact point through said sixth opening.

38. The integrated circuit chip of claim 15, wherein said second polymer layer comprises polyimide.

21. An integrated circuit chip comprising:

a silicon substrate;

a first electroplated gold layer over said silicon substrate;

a polymer layer over said first electroplated gold layer, wherein said polymer layer has a thickness between 2 and 150 micrometers; and

a second electroplated gold layer over said polymer layer, wherein said second electroplated gold layer is connected to said first electroplated gold layer through an opening in said polymer layer, wherein said second electroplated gold layer comprises at least a portion of an inductor.

22. The integrated circuit chip of claim 21, wherein said polymer layer comprises polyimide.

23. The integrated circuit chip of claim 21, wherein said polymer layer comprises benzocyclobutene (BCB).

24. The integrated circuit chip of claim 21 further comprising a dielectric layer between said silicon substrate and said first electroplated gold layer.

25. An integrated circuit chip comprising:

a silicon substrate;

multiple semiconductor devices in or on said silicon substrate, wherein said multiple semiconductor devices comprise a transistor;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a nitride layer;

a third metal layer over said passivation layer, wherein said third metal layer comprises at least a portion, vertically over said passivation layer, of an inductor, wherein said third metal layer comprises electroplated copper; and

a first polymer layer over said third metal layer.

26. The integrated circuit chip of claim 25 further comprising a second polymer layer on said passivation layer, wherein said third metal layer is further on said second polymer layer, wherein said second polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer.

27. The integrated circuit chip of claim 25, wherein said third metal layer is connected to said metallization structure through an opening in said passivation layer, wherein said opening has a width between 0.5 and 30 micrometers.

28. The integrated circuit chip of claim 25, wherein said nitride layer has a thickness between 0.5 and 2 micrometers.

39. The integrated circuit chip of claim 25, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said inductor is connected to said first contact point through said first opening and connected to said second contact point through said second opening.

40. The integrated circuit chip of claim 25, wherein said passivation layer further comprises an oxide layer under said nitride layer.

42. The integrated circuit chip of claim 26, wherein said second polymer layer comprises polyimide.

29. An integrated circuit chip comprising:

a silicon substrate;

multiple semiconductor devices in or on said silicon substrate, wherein said multiple semiconductor devices comprise a transistor;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a separating layer over said metallization structure and over said first and second dielectric layers, wherein said separating layer comprises a nitride layer having a thickness between 0.5 and 2 micrometers;

a third metal layer over said separating layer, wherein said third metal layer comprises at least a portion, vertically over said separating layer, of an inductor, wherein said third metal layer comprises electroplated copper; and

a first polymer layer over said third metal layer.

30. The integrated circuit chip of claim 29 further comprising a second polymer layer on said separating layer, wherein said third metal layer is further on said second polymer layer, wherein said second polymer layer has a thickness between 2 and 150 micrometers and greater than that of said separating layer.

31. The integrated circuit chip of claim 29, wherein said third metal layer is connected to said metallization structure through an opening in said separating layer, wherein said opening has a width between 0.5 and 30 micrometers.

32. The integrated circuit chip of claim 29, wherein a first opening in said separating layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said inductor is connected to said first contact point through said first opening and connected to said second contact point through said second opening.

33. The integrated circuit chip of claim 29, wherein said first polymer layer comprises polyimide.

34. The integrated circuit chip of claim 30, wherein said second polymer layer comprises polyimide.

35. The integrated circuit chip of claim 29, wherein said separating layer further comprises an oxide layer under said nitride layer.

41. The integrated circuit chip of claim 29, wherein said first polymer layer comprises polyimide.

43. An integrated circuit chip comprising:

a silicon substrate;

multiple semiconductor devices in or on said silicon substrate, wherein said multiple semiconductor devices comprise a transistor;

a first dielectric layer over said silicon substrate;

a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a contact point of said first metallization structure, and said contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 30 micrometers; and

a second metallization structure over said passivation layer and over said contact point, wherein said second metallization structure comprises a first portion of gold, wherein said second metallization structure is connected to said contact point through said first opening.

44. The integrated circuit chip of claim 43 further comprising a polymer layer over said passivation layer, wherein a second opening in said polymer layer is over said contact point, wherein said second metallization structure is connected to said contact point further through said second opening.

45. The integrated circuit chip of claim 43 further comprising a polymer layer over said passivation layer.

46. The integrated circuit chip of claim 45, wherein said polymer layer comprises polyimide.

47. The integrated circuit chip of claim 43, wherein said passivation layer further comprises an oxide under said nitride.

48. The integrated circuit chip of claim 43, wherein said first portion of gold is electroplated.

49. The integrated circuit chip of claim 43, wherein said second metallization structure further comprises a second portion of copper under said first portion of gold.

50. The integrated circuit chip of claim 43, wherein said second metallization structure further comprises a second portion of nickel under said first portion of gold.

51. The integrated circuit chip of claim 43, wherein said second metallization structure further comprises a second portion of electroplated copper under said first portion of gold.